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Title	Document #	Date
Standard Practices and Procedures - Thermal Pad Requirements. Item 11.2-748(S)	SPP-022B	Mar 2006
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Standard Overall Profile Height Codes for Packages. RESCINDED, March 2009 Status: RescindedMarch 2009	SPP-017-C	Nov 2004
Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Requirements for Applying Material and Finish Specifications to Selected Mechanical Outlines.	SPP-015
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Registered and Standard Outlines	SPP-013A	Oct 2014
Item 11.2-886(E). This document has been editorially updated to provide template examples. Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783	SPP-024A	Mar 2009
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Procedure for Making Editorial Corrections to Published Documents.	SPP-018
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Pin #1 orientation for TAB Packages.	SPP-005
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Pin #1 Mark Function and Location.	SPP-002
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Pin #1 Mark and Lead-Numbering Convention for Dual-In-Line Packages with Standard and Reverse-Bend Lead Form.	SPP-012
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Package Variation Designators	SPP-025C	Aug 2018
Item No. 11.2-951(S) Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Mold Flash, Interlead Flash, Gate Burrs and Protrusion for Plastic Packages. Item 11.2-379.	SPP-014	Jul 1994
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Module Insertion Procedure for DIMM and miniDIMM Connectors	SPP-023B	Feb 2013
Item 11.11-781(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Metrication.	SPP-003C	Mar 2006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Measuring Stand-off Heights of Packages	SPP-019-A	Jul 2001
Clarification on how to measure A1. Item 11.2-595S Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Lead Finish and base Metal Specification.	SPP-004
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - J Lead; Dimensioning of Lead Contact Points.	SPP-011
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Inclusion of Nominal Dimensions.	SPP-009	Sep 1991
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Inactivation and Rescission.	SPP-016
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Gullwing Lead Dimensioning.	SPP-008	Sep 1991
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Grid Array Terminal Position Numbering	SPP-010B	May 2014
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Document Procedure.	SPP-001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Definition of DAMBAR Protrusion and Intrusion.	SPP-006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Change Record Methodology	SPP-021A	Jan 2006
Item 11.2-710S Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE: Status: Reaffirmed October 2012, September 2018	JESD33B	Feb 2004
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE: Status: Reaffirmed 4/17/23	JESD63	Apr 2023
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD MEASURMENTS OF THE ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR INTEGRATED CIRCUITS Status: RescindedOct-84	JEB6	Jan 1966
Committee(s): JCJEDC
STANDARD MANUFACTURER'S IDENTIFICATION CODE	JEP106BL	Feb 2025
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD:	JESD37A	Aug 2017
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT: Status: ReaffirmedMarch 2001	JESD419-A	Oct 1980
This document contains standard lists of values which are recommended for use in semiconductor device specification and JEDEC Registration Formats. Good reasons should exist in those cases where values are used that are not included in these lists. Formerly known as EIA-419-A, that superseded JEP74 (February 1996). Committee(s): JC-25 Free download. Registration or login required.
STANDARD LIST OF VALUES TO BE USED IN POWER TRANSISTOR DEVICE REGISTRATION AND MINIMUM DIFFERENCES FOR DISCRETENESS OF REGISTRATIONS - SUPERSEDED BY EIA-419-A, February 1996. Status: Rescinded	JEP74	Jan 1969
Committee(s): JC-25
STANDARD FOR THE MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS: Status: ReaffirmedApril 1999, March 2009	JESD435	Apr 1976
This standard specifies the standard for the measurement of small-signal transistor scattering parameters. Formerly known as RS-435 and/or EIA-435 Committee(s): JC-25 Free download. Registration or login required.
STANDARD FOR THE MEASUREMENT OF CRE Status: Reaffirmed April 1981, April 1999, March 2009	JESD340	Nov 1967
This standard offers an easily measured parameter which is one of the significant characteristics in determining the stability of a transistor intended for small-signal operation. The measurement technique allows rapid testing. Its correlation to AC stability will help to establish the interchangeability of a device. Formerly known as RS-340 and/or EIA-340. Committee(s): JC-25 Free download. Registration or login required.
STANDARD FOR SELENIUM SURGE SUPPRESSORS:	TENTSTD12	Nov 1973
The suppresser furnished under this standard shall be a product that has been tested and meets the definitions and minimum requirements specified herein. Committee(s): JC-22.5
STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OF SEMICONDUCTOR DIODES: Status: ReaffirmedApril 2005	JESD286-B	Feb 2000
This method updates the standard procedure for characterizing the switching of signal or switching diodes when a step function of forward current is applied. The objective is to provide a standard so that accurate comparisons can be made. Formerly known as EIA-286-A (February 1991), ANSI/EIA-286-A-1991. Became JESD286-B after revision, February 2000. Committee(s): JC-22.4 Free download. Registration or login required.
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT: Status: Rescinded January 2025	JESD38	Dec 1995
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:	JESD55	May 1996
The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:	JESD52	Nov 1995
This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC:	JESD18-A	Jan 1993
The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices. Committee(s): JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION	JESD82-5	Jul 2002
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES:	JESD7-A	Aug 1986
This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers. Committee(s): JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES: Release Number: Pt 2	JESD20	Jan 1990
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES: Release Number: Pt 1	JESD20	Jan 1990
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:	JESD54	Feb 1996
The purpose is to provide a standard of BiCMOS Logic series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:	JESD73-4	Nov 2001
This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Committee(s): JC-40, JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:	JESD73-3	Nov 2001
This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Committee(s): JC-40, JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:	JESD73-1	Aug 2001
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:	JESD73-2	Aug 2001
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES:	JESD80	Nov 1999
The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:	JESD64-A	Oct 2000
The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:	JESD82-4B.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-18A	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-15	Nov 2005
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-21	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION	JESD82-8.01	Feb 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR CHAIN DESCRIPTION FILE:	JESD32	Jun 1996
This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the configuration of a programming chain made up of devices that can be connected in some serial fashion. No assumptions are made about how data is used by the device, nor about the nature or configuration of the control signals that affect programming. It will support devices configured using electrically-erasable(EE), Flash, SRAM, or any other reconfigurable cell. For devices programmed via an IEEE programmable devices in the same chain. Committee(s): JC-42.1 Free download. Registration or login required.
STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C. Status: RescindedApr-85	JEP102	Jan 1978
Committee(s): JC-42
STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:	JESD36	Jun 1996
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses. Committee(s): JC-40 Free download. Registration or login required.
STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:	JESD76-3	Aug 2001
This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):	JESD76-1	Jun 2001
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.

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Standards & Documents Search

Standard Practices and Procedures - Thermal Pad Requirements. Item 11.2-748(S)

Standard Practices and Procedures - Standard Overall Profile Height Codes for Packages. RESCINDED, March 2009

Standard Practices and Procedures - Requirements for Applying Material and Finish Specifications to Selected Mechanical Outlines.

Standard Practices and Procedures - Registered and Standard Outlines

Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783

Standard Practices and Procedures - Procedure for Making Editorial Corrections to Published Documents.

Standard Practices and Procedures - Pin #1 orientation for TAB Packages.

Standard Practices and Procedures - Pin #1 Mark Function and Location.

Standard Practices and Procedures - Pin #1 Mark and Lead-Numbering Convention for Dual-In-Line Packages with Standard and Reverse-Bend Lead Form.

Standard Practices and Procedures - Package Variation Designators

Standard Practices and Procedures - Mold Flash, Interlead Flash, Gate Burrs and Protrusion for Plastic Packages. Item 11.2-379.

Standard Practices and Procedures - Module Insertion Procedure for DIMM and miniDIMM Connectors

Standard Practices and Procedures - Metrication.

Standard Practices and Procedures - Measuring Stand-off Heights of Packages

Standard Practices and Procedures - Lead Finish and base Metal Specification.

Standard Practices and Procedures - J Lead; Dimensioning of Lead Contact Points.

Standard Practices and Procedures - Inclusion of Nominal Dimensions.

Standard Practices and Procedures - Inactivation and Rescission.

Standard Practices and Procedures - Gullwing Lead Dimensioning.

Standard Practices and Procedures - Grid Array Terminal Position Numbering

Standard Practices and Procedures - Document Procedure.

Standard Practices and Procedures - Definition of DAMBAR Protrusion and Intrusion.

Standard Practices and Procedures - Change Record Methodology

STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE:

STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:

STANDARD MEASURMENTS OF THE ELECTRICAL CHARACTERISTICS OF SEMICONDUCTOR INTEGRATED CIRCUITS

STANDARD MANUFACTURER'S IDENTIFICATION CODE

STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD:

STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT:

STANDARD LIST OF VALUES TO BE USED IN POWER TRANSISTOR DEVICE REGISTRATION AND MINIMUM DIFFERENCES FOR DISCRETENESS OF REGISTRATIONS - SUPERSEDED BY EIA-419-A, February 1996.

STANDARD FOR THE MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS:

STANDARD FOR THE MEASUREMENT OF CRE

STANDARD FOR SELENIUM SURGE SUPPRESSORS:

STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OF SEMICONDUCTOR DIODES:

STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:

STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:

STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC:

STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES:

STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:

STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES:

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:

STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:

STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION

STANDARD FOR CHAIN DESCRIPTION FILE:

STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:

STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):

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