Global Standards for the Microelectronics Industry
Standards & Documents Search
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Annex D, Raw Card D, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 31 |
MODULE4.20.25.D | Mar 2022 |
This specification defines the electrical and mechanical requirements for Raw Card D, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.60. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package |
MO-343B | Mar 2022 |
Designator: PDSO-N2-I#-R#x#Z#-CturET0p04
Item: 11.11-1000, Access STP File for MO-343B
Cross Reference: DG4.20
Patents(): Nexperia BV: US8809121 B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Dual Connector |
SO-025B | Mar 2022 |
Designator: PDXC-PP2-I8p9-R107p6xp15Z26p0-DD2p95x1p1
Item: 11.14-208, Access STP Files for SO-025B Cross Reference: TBD Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Board Mount |
SO-030A | Feb 2022 |
Designator: PBCX-K4_...
Item: 11.14-211,
Access STP Files for SO-030A Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - 262 Pin DDR5 SODIMM, 0.50 mm Pitch Package |
MO-337B | Feb 2022 |
Designator: PDMA-N262-I0p5-R69p6x3p7Z30p15R2p55x02p35
Item: 11.14-207,
Access STP Files for MO-337B
Cross Reference: SO-024 Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Specification |
JESD305 | Jan 2022 |
This standard defines the electrical and mechanical requirements for 288-pin, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM) and Load Reduced (LRDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These 288-pin Registered and Load Reduced DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Item 2273.07. Committee(s): JC-45.1 Free download. Registration or login required. |
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TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES |
JESD22-A120C | Jan 2022 |
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - Enclosure Form Factor for Automotive SSD Connector, Cable Mount |
SO-029A | Jan 2022 |
Designator: PBXC-K4_D#p##-MR36p05x14p5Z10p25-HS
Item: 11.14-210, Access STP Files for SO-029A Cross Reference: MO-348 Committee(s): JC-11.14 Free download. Registration or login required. |
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Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices |
JEP151A | Jan 2022 |
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications.
Committee(s): JC-14.1 Free download. Registration or login required. |
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DDR5 Buffer Definition (DDR5DB01) - Rev. 1.1 |
JESD82-521 | Dec 2021 |
This standard defines standard specifications for features and functionality, DC & AC interface parameters and test loading for definition of the DDR5 data buffer for driving DQ and DQS nets on DDR5 LRDIMM applications. The purpose is to provide a standard for the DDR5DB01 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 323.98K Committee(s): JC-40.4 Free download. Registration or login required. |
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Backup Energy Module Standard for NVDIMM Memory Devices (BEM) |
JESD315 | Dec 2021 |
This standard defines the functional requirements of Backup Energy Module (BEM), henceforth referred to as BEM in this standard. This module shall be used to provide backup power to the Industry Defined Storage Array Controller Cards and NVDIMM-n as applicable. All standards are applicable under all operating conditions unless otherwise stated. Item 2279.03 Committee(s): JC-45 Free download. Registration or login required. |
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Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets |
JEP187 | Dec 2021 |
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required. |
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Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 |
JEP186 | Dec 2021 |
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required. |
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Serial Interface for Data Converters |
JESD204C.1 | Dec 2021 |
This standard describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the document. Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.35 mm x 0.40 mm Pitch Rectangular Family Package |
MO-350A | Nov 2021 |
Designator: PBGA-B#[#]_I0p35... Item 11-998 Committee(s): JC-11.11 Free download. Registration or login required. |
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SEMICONDUCTOR WAFER AND DIE BACKSIDE EXTERNAL VISUAL INSPECTION |
JESD22-B118A | Nov 2021 |
This inspection method is for product semiconductor wafers and dice prior to assembly. This test method defines the requirements to execute a standardized external visual inspection and is a non-invasive and nondestructive examination that can be used for qualification, quality monitoring, and lot acceptance. Committee(s): JC-14.1 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32S865 AND SSTUA32D865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-19A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S865 and SSTUA32D865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. This is a minor editor revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-10A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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Registration - Shipping and Handling Tray for DDR5 DIMM Microelectronic Assembly |
CO-036B | Oct 2021 |
Designator: N/A Item: 11.5-997, Access STP Files for CO-036B Cross Reference: N/A Committee(s): JC-11.5 Free download. Registration or login required. |
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REGISTRATION - Battery Cell R/A SMT Type Connector, 1.2 mm Pitch |
SO-028A | Oct 2021 |
Designator: PSXC-L6_I1p2-R11p6x5p85Z2p07-R0p3x0p6ET0p07 Item: 11.14-198, Access STP Files for SO-028A Cross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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REGISTRATION - Battery Cell R/A T/H Type Connector, 1.2 mm Pitch |
SO-026A | Oct 2021 |
Designator: PSXC-P6_I1p2-R11p6x5p85Z2p0-R0p3x0p31H1p16 Item: 11.14-198, Access STP Files for SO-026A Cross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS |
JESD82-9B.01 | Oct 2021 |
This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS: |
JESD82-4B.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS |
JESD82-16A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Free download. Registration or login required. |
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DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-14A.01 | Oct 2021 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required. |
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Registration - Battery Cell Wire Side Connector, 1.2 mm pitch |
SO-027A | Sep 2021 |
Designator: PBXC-q6_i1P2-r7P9X4P25z1P58 Item: 11.14-199, Access STP Files for SO-027A Cross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE |
JESD89-3B | Sep 2021 |
This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER. Committee(s): JC-14.1 Free download. Registration or login required. |
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Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE |
JESD251-1.01 | Sep 2021 |
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 Committee(s): JC-42.4 Free download. Registration or login required. |
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MEASUREMENT AND REPORTING OF ALPHA PARTICLE AND TERRESTRIAL COSMIC RAY INDUCED SOFT ERRORS IN SEMICONDUCTOR DEVICES |
JESD89B | Sep 2021 |
This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER) testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and accelerated testing procedures are described. At terrestrial, Earth-based altitudes, the predominant sources of radiation include both cosmic-ray radiation and alpha-particle radiation from radioisotopic impurities in the package and chip materials. An overall assessment of a deviceís SER is complete, only when an unaccelerated test is done, or accelerated SER data for the alpha-particle component and the cosmic-radiation component has been obtained. Free download. Registration or login required. |
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DDR5 REGISTERING CLOCK DRIVER DEFINITION (DDR5RCD01) |
JESD82-511 | Aug 2021 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD01 Device ID is DID = 0x0051. Committee(s): JC-40.4 Free download. Registration or login required. |
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ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0 |
JESD253.01 | Aug 2021 |
This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. This is a minor editorial revision detailed in Annex D. Committee(s): JC-64.8 Free download. Registration or login required. |
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GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES |
JESD31F | Aug 2021 |
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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TEST METHOD FOR REAL-TIME SOFT ERROR RATE |
JESD89-1B | Jul 2021 |
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Free download. Registration or login required. |
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TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE |
JESD89-2B | Jul 2021 |
This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source. Free download. Registration or login required. |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |
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METHODS FOR CALCULATING FAILURE RATES IN UNITS OF FITS |
JESD85A | Jul 2021 |
This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference to the way failure rates are calculated. Committee(s): JC-14.3 Free download. Registration or login required. |
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DDR4 SDRAM STANDARD |
JESD79-4D | Jul 2021 |
This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H Committee(s): JC-42.3C Available for purchase: $284.00 Add to Cart Paying JEDEC Members may login for free access. |
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Registration - Metal Enclosure for SSD Devices, E1.S and M.2 |
MO-348A | Jul 2021 |
Designator: MMXH-R(##)x36p75Z(##) Item: 11.14-205, Access STP Files for MO-348A Cross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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184 Pin, PC-1600/PC-2100 DDR SDRAM Unbuffered DIMM Design Specification. |
MODULE4.20.5 | May 2021 |
Release No. 31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification |
MODULE4.20.8 | May 2021 |
Release No. 31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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PC-1600/PC-2100 DDR SDRAM Registered DIMM Design Specification (184 Pin) |
MODULE4.20.4 | May 2021 |
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family |
MODULE4.5.14 | May 2021 |
Release No. 31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered SDR SDRAM DIMM Family |
MODULE4.5.11 | May 2021 |
Release No.31 This revision contains terminology updates only. Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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HIGHLY ACCELERATED TEMPERATURE AND HUMIDITY STRESS TEST (HAST) |
JESD22-A110E.01 | May 2021 |
The purpose of this test method is to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs severe conditions of temperature, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors which pass through it. This is a minor editorial edit to JESD22A110E, July 2015 approved by the formulating committee. Committee(s): JC-14.1 Free download. Registration or login required. |
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ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST |
JESD22-A118B.01 | May 2021 |
The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required. |
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PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2 |
MODULE4.20.7 | May 2021 |
Release 31. Item 2029.04 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES |
JESD260 | Apr 2021 |
This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard. Committee(s): JC-42.4 Free download. Registration or login required. |
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SERIAL FLASH RESET SIGNALING PROTOCOL |
JESD252.01 | Apr 2021 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required. |
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Registration - 84 Pin DDIMM, 0.60 mm Pitch Microelectronic Assembly |
MO-335A | Apr 2021 |
Designator: PDMA-N84-I0p6-R85p13xY#Z#R1p98x0p43
Item: 11.14-191, Access STP Files for MO-335A Cross Reference: N/A Committee(s): JC-11.14 Free download. Registration or login required. |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS |
JEP178 | Apr 2021 |
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required. |
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Design Requirements - Wafer Level Ball Grid Arrays (WLBGA). |
DR-4.18A.01 | Apr 2021 |
Item 11.2-965(E) Free download. Registration or login required. |
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GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION |
JEP184 | Mar 2021 |
The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well. Committee(s): JC-70.2 Free download. Registration or login required. |
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FLIP CHIP TENSILE PULL |
JESD22-B109C | Mar 2021 |
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - 39 Pin Removable Memory, 1.00 mm Pitch Microelectronic Assembly |
MO-347A | Mar 2021 |
Designator: PBMA-N32[39]_Ip0-R14p1x18p1Z1p65-R0p71x1p1
Item: 11.11-987, Access STP Files for MO-347A Cross Reference: N/A Patents(): Kioxia: 1705380 Committee(s): JC-11.11 Free download. Registration or login required. |
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SYSTEM LEVEL ROWHAMMER MITIGATION |
JEP301-1 | Mar 2021 |
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required. |
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NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION |
JEP300-1 | Mar 2021 |
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required. |