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Title	Document #	Date
Bit Wide ECL SRAM	SRAM3.7.2	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Nibble Wide SRAM	SRAM3.7.3	Dec 1995
Release No.5 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SRAM	SRAM3.7.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide ECL SRAM	SRAM3.7.6	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Eight Byte Wide (X64/72) MOS SRAM	SRAM3.7.9	Jun 2007
Release No. 16A. Item 1480.05 and 1531.04 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide TTL and MOS SRAM	SRAM3.7.7	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Double Word Wide MOS SRAM	SRAM3.7.8	Apr 2007
Release No. 16. Item 1541.03 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
NVRAM, Nonvolatile RAM	NVRAM3.6	Dec 1991
Release No.1 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20	NVRAM3.6.3	Feb 2009
Release No. 18A Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EPROM Introduction	EPROM3.4	Jul 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide EPROM	EPROM3.4.2	Jun 1999
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide	EPROM3.4.1	Jul 1997
Release No.9 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM Extended Features	EEPROM3.5.3	Jan 2005
Release No.14 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM Introduction	EEPROM3.5	Jul 1997
Release No.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide EEPROM	EEPROM3.5.1	Aug 2005
Release No. 14 Committee(s): JC-42.4, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
EEPROM, Word Wide	EEPROM3.5.2	Jun 2007
Release No. 16. Item 1704.1 Committee(s): JC-42, JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Dynamic Random Access Memory (DRAM) Table of Contents	DRAM3.9.TOC	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide DRAM	DRAM3.9.1	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Nibble Wide DRAM	DRAM3.9.2	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide DRAM	DRAM3.9.4	Jul 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide DRAM	DRAM3.9.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DRAM Operational Features	DRAM3.9.5	Feb 2000
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).	DR-4.18A.01	Apr 2021
Item 11.2-965(E) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).	DR-4.22C.02	Mar 2011
Item 11.2-839(R) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine pitch, Rectangular Ball Grid Array Packages (FRBGA). Status: RescindedFebruary 2015	DR-4.6D.01	Jul 2012
This outline has been replaced by Design Registration 4.5J and Design Registration 4.27C. Item 11.2-838(S), 11-893R, 11-894R Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page
Design Requirements - Ball Grid Array Package (BGA)	DR-4.27F.01	Nov 2018
Ball Pitch = 0.65, 0.75 and 0.80 mm, Body sizes >21mm. (For body sizes ≤ 21mm see Design Registration 4.5) Item 11.2-969E. Editorial Change Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM	DR-4.5O	Nov 2023
BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM Item 2-1038 Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Micropillar Grid Array (MPGA)	DR-4.26B	Nov 2015
Item 11.2-845(R) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA)	DR-4.14J.01	Feb 2019
Item 11.2-948E Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
TSE2002 Serial Presence Detect with Thermal Sensor	PRN09-NV2	Jul 2009
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 1756.00A Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR3 DIMM Label	PRN09-NM4	Oct 2009
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 2099.01b Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR3 Unbuffered Mini-DIMM, Annex B	PRN11-NM2	Jun 2011
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release JESD21C. Item 2201.10 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR3 Unbuffered Mini-DIMM, Annex A	PRN11-NM1	Jun 2011
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of JESD21C. Item 2207.11 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)	PRN13-NM1	Oct 2013
Item No. 2229.01 (JC-45.3-11-523, JCB-11-102) Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)	PRN13-NM3	Oct 2013
Item No. 2207.14 (JC-45.1-12-284, JCB-12-63) Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR4 UDIMM Design Specification Annex D	PRN14-NM1	Feb 2014
Item 2231.09 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PC4-RDIMM_090_Annex-F	PRN14-NM10	May 2014
Item 2241.11 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Design Requirements - Quad Flatpack	DG-4.4A	Jun 2000
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Generic Matrix Tray for Handling and Shipping, includes addition of optional side-wall bar code feature.	DG-4.10D	Oct 2002
Item 11.2-615s Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Metric Small Outline J-Leaded Package Design Guide	DG-4.13	Aug 1996
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Thin Small Outline Package, TSOP - Type 2.	DG-4.15B	May 2004
Item 11.2-675(s) Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.	DG-4.16A	Feb 1998
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.	DG-4.17C	Jul 2008
Item 11.2-791(S) Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Quad No-Lead Staggered and Inline Multi-Row Packages (with optional thermal enhancements). QFN.	DG-4.19D	May 2007
Item 11.2-765(s) Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Punch-Singulated, Fine Pitch, Square, Very Thin and Very Very Thin Profile, Leadframe-Based Quad No-Lead Staggared Dual-Row Packages, (with optional Thermal Enhancements) QFN.	DG-4.23A	Nov 2005
Item 11.2-728(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (with Optional Thermal Enhancements). QFP-N/SO-N.	DG-4.8C	Sep 2006
Item 11.2-713(s) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Generic Matrix Tray for Handling and Shipping (Low Stacking Profile for BGA Packages).	DG-4.9A	Mar 2000
Item 11.2-539S Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.	DG-4.7F	Jan 2014
Item 11.2-829R Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Internal Stacking Module, Land Grid Array Packages with External Interconnect Terminals (ISM).	DG-4.21A	Feb 2007
Item 11.2-699(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - General Requirements	DG-4.2	Jan 1980
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)	DG-4.25B	Aug 2016
This Design Requirement defines the symbols, definitions, algorithms, and specified dimensions and tolerances for Fine-pitch, LGA packages. The guidelines defined are based on hard metric dimensions and adhere to the geometric dimensioning and tolerancing principles defined in ASME Y14.5M-1994. Item 11.2-896(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)	DG-4.24B	Aug 2016
Item 11.2-850(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).	DG-4.20F	Sep 2016
Item 11.2-820(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
IPC/JEDEC-9704A: PRINTED WIRING BOARD (PWB) STRAIN GAGE TEST GUIDELINE	JS9704A	Jan 2012
This document describes specific guidelines for strain gage testing for Printed Wiring Board (PWB)assemblies. The suggested procedures enables board manufacturers to conduct required strain gage testing independently, and provides a quantitative method for measuring board flexure, and assessing risk levels. The topics covered include: Test setup and equipment; requirements; Strain measurement; Report format Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IPC/JEDEC-9703: MECHANICAL SHOCK TEST GUIDELINE FOR SOLDER JOINT RELIABILITY Status: Reaffirmed May 2014, May 2019	JS9703	Mar 2009
This document establishes mechanical shock test guidelines for assessing solder joint reliability of Printed Circuit Board (PCB) assemblies from system to component level. Committee(s): JC-14.1 Free download. Registration or login required.
Definition of “Low-Halogen” For Electronic Products	JS709D	Jan 2024
This standard provides terms and definitions for “low-halogen” electronic products. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)	JS9702	Jun 2004
This publication specifies a common method of establishing the fracture resistance of board-level device interconnects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/fail requirements are typically specific to each device application and are outside the scope of this document. This version contains Addendum 1, May 2015, reposted 8/15/2016. Committee(s): JC-14.1 Free download. Registration or login required.
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL	JS-001-2024	Oct 2024
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jun 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Numerical Analysis Guidelines for Microelectronics Packaging Design and Reliability	IPC/JEDEC9301-2018	Dec 2018
This document is an effort to standardize and document some of the basic tenets of a typical Finite Element Analysis (FEA) model. The intent of this document is to help educate new designers (and in some cases even experienced designers) on the basic information and best practices that should be captured and provided to technical reviewers of the results of FEA data. Committee(s): JC-14.1 Free download. Registration or login required.

Standards & Documents Search

Bit Wide ECL SRAM

Nibble Wide SRAM

Byte Wide SRAM

Byte Wide ECL SRAM

Eight Byte Wide (X64/72) MOS SRAM

Word Wide TTL and MOS SRAM

Double Word Wide MOS SRAM

NVRAM, Nonvolatile RAM

Low Power Double Data Rate (LPDDR) Non-Volatile Memory (NVM) (Item 1674.17, 1674.16, 1674.20

EPROM Introduction

Word Wide EPROM

Byte Wide

EEPROM Extended Features

EEPROM Introduction

Byte Wide EEPROM

EEPROM, Word Wide

Dynamic Random Access Memory (DRAM) Table of Contents

Bit Wide DRAM

Nibble Wide DRAM

Word Wide DRAM

Byte Wide DRAM

DRAM Operational Features

Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).

Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).

Design Requirements - Fine pitch, Rectangular Ball Grid Array Packages (FRBGA).

Design Requirements - Ball Grid Array Package (BGA)

Design Requirements - BALL GRID ARRAY PACKAGE BALL PITCH ≤ 0.80 MM BODY SIZES ≤ 21 MM

Design Requirements - Micropillar Grid Array (MPGA)

Design Requirements - Ball Grid Array Package (BGA)

TSE2002 Serial Presence Detect with Thermal Sensor

DDR3 DIMM Label

DDR3 Unbuffered Mini-DIMM, Annex B

DDR3 Unbuffered Mini-DIMM, Annex A

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)

DDR4 UDIMM Design Specification Annex D

PC4-RDIMM_090_Annex-F

Design Requirements - Quad Flatpack

Design Requirements - Generic Matrix Tray for Handling and Shipping, includes addition of optional side-wall bar code feature.

Design Requirements - Metric Small Outline J-Leaded Package Design Guide

Design Requirements - Thin Small Outline Package, TSOP - Type 2.

Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.

Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.

Design Requirements - Quad No-Lead Staggered and Inline Multi-Row Packages (with optional thermal enhancements). QFN.

Design Requirements - Punch-Singulated, Fine Pitch, Square, Very Thin and Very Very Thin Profile, Leadframe-Based Quad No-Lead Staggared Dual-Row Packages, (with optional Thermal Enhancements) QFN.

Design Requirements - Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (with Optional Thermal Enhancements). QFP-N/SO-N.

Design Requirements - Generic Matrix Tray for Handling and Shipping (Low Stacking Profile for BGA Packages).

Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.

Design Requirements - Internal Stacking Module, Land Grid Array Packages with External Interconnect Terminals (ISM).

Design Requirements - General Requirements

Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)

Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)

Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).

IPC/JEDEC-9704A: PRINTED WIRING BOARD (PWB) STRAIN GAGE TEST GUIDELINE

IPC/JEDEC-9703: MECHANICAL SHOCK TEST GUIDELINE FOR SOLDER JOINT RELIABILITY

Definition of “Low-Halogen” For Electronic Products

IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702)

JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

Numerical Analysis Guidelines for Microelectronics Packaging Design and Reliability

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