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This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5.

Committee(s): JC-42.3

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Committee(s): JC-13.2

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This publication provides an index to terms that are defined in certain JEDEC publications. It is intended to promote the uniform use of these terms and their definitions while reducing the proliferation of new definitions for old terms.

Committee(s): JC-10

This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis.

Committee(s): JC-14, JC-14.2

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This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535.

Committee(s): JC-13, JC-13.2

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This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories

Committee(s): JC-42.6

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This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases.

Committee(s): JC-14, JC-14.3

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The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

Committee(s): JC-42, JC-42.3

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Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry.

Committee(s): JC-14.3

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This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and
reliability testing. These tests are used frequently in qualifying integrated circuits as a new
product, a product family, or as products in a process which is being changed.

Committee(s): JC-14.3

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The publication provides methodologies for measurements to qualify a new semiconductor wafer process.

Committee(s): JC-14, JC-14.2

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This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches.

Committee(s): JC-70.1

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This document is intended for use in the GaN power semiconductor and related power electronic industries and provides guidelines for test methods and circuits to be used for continuous-switching tests of GaN power conversion devices.

Committee(s): JC-70.1

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RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01.

Committee(s): JC-42

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The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well.

Committee(s): JC-70.2

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This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements.

Committee(s): JC-14.3

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This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets.

Committee(s): JC-70.2

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This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup.

Committee(s): JC-70.2

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This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry.

Committee(s): JC-14, JC-14.1

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This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric.

Committee(s): JC-70, JC-70.2

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-16

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-15

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This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces.

Committee(s): JC-14, JC-14.3

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This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches.

Committee(s): JC-70, JC-70.1

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This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including:

• JEP30-A101v2-0-3 (Assembly Process),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-E101v4-1-0 (Electrical),
  
  • Committees: JC-11, JC-11.2, JC-16
• JEP30-P101v7-0-0 (Package),
  
  • Committees: JC-11, JC-11.2
• JEP30-S101v1-1-0 (Supply Chain),
  
  • Committees: JC-11, JC-11.2, JC-14
• JEP30-T101v2-0-3 (Thermal)
  
  • Committees: JC-11, JC-11.2, JC-15
• JEP30-D10v4-0-0 (Types Dictionary)
  
  • Committees: JC-11, JC-11.2

This will enable the user to validate the schemas. For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16

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This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results.

Committee(s): JC-70, JC-70.2

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The purpose of this document is to provide manufacturers and users with standardized methods for handling, packing, shipping, and use of moisture/reflow and process sensitive devices that have been classified to the levels defined in J-STD-020 or J-STD-075. These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and  damage-free reflow can be achieved. The dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date.

Committee(s): JC-14, JC-14.1

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The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations.

Committee(s): JC-14, JC-14.1

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