Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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POWER MOSFET ELECTRICAL DOSE RATE TEST METHOD:Status: ReaffirmedApril 1999 |
JEP115 | Aug 1989 |
The purpose of this Test Method is to establish electrical criteria for comparing and specifying power MOSFET performance under high dose rate radiation. Committee(s): JC-25 Free download. Registration or login required. |
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CMOS SEMICUSTOM DESIGN GUIDELINES: |
JEP116 | Nov 1991 |
The design of ASIC circuits is becoming a significant part of system or product design, yet many problems continue to exist in current design practice. The guidelines in this document provide an explanation of common ASIC design problems and concerns and where possible offer solutions. Committee(s): JC-44 Free download. Registration or login required. |
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GUIDELINES FOR USER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERS - SUPERSEDED BY JESD46, August 1997.Status: Rescinded |
JEP117 | Apr 1994 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING |
JEP118A | Dec 2018 |
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required. |
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REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION: |
JEP121B | Dec 2020 |
The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufacturer in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. Free download. Registration or login required. |
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GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS: |
JEP126 | May 1996 |
This publication provides a guideline to suppliers of IC components with a template for documenting the numerical simulation assumptions. In addition this guideline also suggests a model environment to reference when comparing various packages or component suppliers. This publication should improve the communication between the package model suppliers. This publication should improve the communication between the package model supplier and the end user. Committee(s): JC-15.2 Free download. Registration or login required. |
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GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999.Status: RescindedNovember 1999 |
JEP124 | Dec 1995 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING:Status: Rescinded September 2021 (JC-14.2-21-182) |
JEP128 | Nov 1996 |
This guide has been replaced by JESD241: September 2021. Committee(s): JC-14.2 |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997.Status: ElevatedSeptember 1997 |
JEP129 | Feb 1997 |
Committee(s): JC-15.1 Free download. Registration or login required. |
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Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel) |
JEP130C | Feb 2023 |
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Free download. Registration or login required. |
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PROCESS CHARACTERIZATION GUIDELINE |
JEP132A.01 | Dec 2022 |
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required. |
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GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS: |
JEP134 | Sep 1998 |
The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis. Committee(s): JC-14.6 Free download. Registration or login required. |
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SIGNATURE ANALYSIS: |
JEP136 | Jul 1999 |
Signature Analysis is a method to reduce the number of comprehensive physical failure analyses by the application of statistical inference techniques. The purpose of this document is to promote a common definition of Signature Analysis by inference, using the same statistical techniques, and to recognize that it is formal means of doing failure analysis. Committee(s): JC-14.6 Free download. Registration or login required. |
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COMMON FLASH INTERFACE (CFI) IDENTIFICATION CODES: |
JEP137B | May 2004 |
This publication is a companion document to the Common Flash Interface (CFI) standard, JESD68, which outlines the device and host system software interrogation handshake. JEP137 documents ID Code assignments for: 1)) the Algorithm-specific Command Set and Control Interfaces and 2) the Device Interfaces. It is published as needed when additions are made to either of these lists of codes. To make a request for an ID Code please contact the JEDEC Office at (703)907-7558. Committee(s): JC-42.4 Free download. Registration or login required. |
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USER GUIDELINES FOR IR THERMAL IMAGING DETERMINATION OF DIE TEMPERATURE: |
JEP138 | Sep 1999 |
The purpose of these user guidelines is to provide background and an example for the use of an infrared (IR) microscope to determine die temperature of electronic devices for calculations such as thermal resistance. Committee(s): JC-25 Free download. Registration or login required. |
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TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS:Status: ReaffirmedSeptember 1981, April 1999 |
JEP65 | Dec 1967 |
This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with formats developed for device registration and defining data. Committee(s): JC-25 Free download. Registration or login required. |
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PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS:Status: ReaffirmedSeptember 1981, April 1999 |
JEP69-B | Nov 1973 |
This publication indicates preferred pinouts for FETs in various package designs. Committee(s): JC-25 Free download. Registration or login required. |
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LETTER SYMBOLS USED WITH INFRARED DEVICES - INCORPORATED INTO JESD77-A.Status: Rescinded |
JEP75 | Aug 1984 |
Committee(s): JC-10 Free download. Registration or login required. |
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LIFE TEST METHODS FOR PHOTOCONDUCTIVE CELLS: |
JEP79 | Sep 1969 |
This publication is for photoconductive cells sensitive primarily in the visible and near infrared region. Free download. Registration or login required. |
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RECOMMENDED PRACTICE FOR MEASUREMENT OF TRANSISTOR LEAD TEMPERATURE: |
JEP84A | Jun 2004 |
This publication covers recommended methods for measurement of transistor lead temperatures under various load conditions. The techniques described are sufficiently accurate for most applications. Committee(s): JC-25 Free download. Registration or login required. |
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THERMAL RESISTANCE FOR TEST METHODS FOR SIGNAL DIODES - SUPERSEDED BY EIA-531, July 1986. See JESD531, April 2002.Status: Rescinded |
JEP90 | Sep 1983 |
Committee(s): JC-22.4 Free download. Registration or login required. |
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GLOSSARY OF MICROELECTRONIC TERMS, DEFINITIONS, AND SYMBOLS: ELEVATED TO JESD99, June 1985.Status: Rescinded |
JEP99 | Jul 1977 |
Committee(s): JC-10 Free download. Registration or login required. |
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REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES: |
JEP104C.01 | May 2003 |
This publication provides a quick reference to the letter symbols and corresponding terms that are defined in JESD77-B, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices; JESD99-A, Terms, Definitions, and Letter Symbols for Microelectronic Devices, and JESD100-B, Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits. It is intended to simplify interpretation of data sheets and specifications and to promote the uniform use of these symbols. The symbols relate to ratings and characteristics found in data sheets and other specifications. Some abbreviations used in lieu of symbols are also included. The newly added Annex B is provided as an aid to determining what symbol should be used and is organized by term, whereas the main body of the publication is organized by symbol or abbreviation as in previous versions. This version contains minor revisions Committee(s): JC-10 Free download. Registration or login required. |
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GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM: |
JEP145 | Feb 2003 |
This publication is intended as a guideline to establish procedures, consideration and common practices that will allow a manufacturer, an application entity, a system designer and other interested parties to define current capability limitations in the leads of components and power systems with semiconductor components. This is a guideline, not a standardized method, it was developed over several years to clarify questions that had been posed to committee members in their respective engineering functions. Committee(s): JC-25 Free download. Registration or login required. |
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PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA): |
JEP147 | Oct 2003 |
This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. Free download. Registration or login required. |
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APPLICATION THERMAL DERATING METHODOLOGIES: |
JEP149.01 | Jan 2021 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |
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DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION |
JEP179 | Jun 2006 |
The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. Committee(s): JC-42.3 Free download. Registration or login required. |
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RELATIVE SPECTRAL RESPONSE CURVES FOR SEMICONDUCTOR INFRARED DETECTORS: |
JEP78 | Oct 1969 |
The intent of this publication is to facilitate the specification of infrared detector diodes, particularly in conjunction with the preparation of data for JEDEC type registration. Committee(s): JC-COUN Free download. Registration or login required. |
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STANDARD LIST OF VALUES TO BE USED IN POWER TRANSISTOR DEVICE REGISTRATION AND MINIMUM DIFFERENCES FOR DISCRETENESS OF REGISTRATIONS - SUPERSEDED BY EIA-419-A, February 1996.Status: Rescinded |
JEP74 | Jan 1969 |
Committee(s): JC-25 |
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FORWARD TURN-ON TIME MEASUREMENT ON SEMI-DIODES - INCORPORATED INTO EIA-282-A.Status: Rescinded |
JEP87 | Jan 1992 |
Committee(s): JC-22.2 |
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STANDARD FOR 64K x 1 DYNAMIC RAM - SUPERSEDED BY JESD21-C.Status: RescindedApr-85 |
JEP102 | Jan 1978 |
Committee(s): JC-42 |
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TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C.Status: RescindedJun-96 |
JEP111 | Jan 1986 |
RECOMMENDED PRACTICE FOR DUAL DIMENSIONINGStatus: Rescinded |
JEP86-A | Jan 1976 |
Committee(s): JC-11 |
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THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORSStatus: Rescinded |
JEP88 | Jan 1974 |
Committee(s): JC-22.1 |
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ANNUAL UPDATING SERVICE: |
JEP95 AUS | Jan 2000 |
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. Committee(s): JC-11 |
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GUIDELINES FOR NONDESTRUCTIVE PULL TESTING OF WIRE BONDS ON HYBRID DEVICESStatus: Rescinded |
JEP96 | Jan 1977 |
Committee(s): JC-13.5 |
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MICROELECTRONIC DEVICE TYPE ASSIGNMENTSStatus: RescindedJun-92 |
JEP93 | Jan 1975 |
Committee(s): JCJEDC |
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GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS: |
JEP123 | Oct 1995 |
The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 provided the forum where various methods were discussed and commonality in approach emerged. The result is that today we have relatively consistent results in measuring and reporting electrical package parameters, as well as specialized tools (e.g., the IPA-510, the interconnect parameter analyzer) which were developed to support the methodology. Free download. Registration or login required. |
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GUIDE FOR THE PRODUCTION AND ACQUISITION OF RADIATION-HARDNESS ASSURED MULTICHIP MODULES AND HYBRID MICROCIRCUITS: |
JEP133C | Jan 2010 |
A revised and expanded publication for suppliers and users of radiation hardness assured (RHA) multichip modules (MCMs) and hybrid microcircuits, is now available. The document provides guidance as to how to achieve, maintain and ensure required levels of radiation-hardness given the fact that the constituent dice can have different levels of hardness assurance. It also describes how to deal with the various radiation hardness situations that an MCM/Hybrid developer, procuring activity or user will encounter. The guide is intended to supplement three relevant performance specifications: MIL-PRF-38534, MIL-PRF-38535 and MIL-PRF-19500. Committee(s): JC-13.5, JC-13.4 Free download. Registration or login required. |
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JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS: |
JEP95 | Jan 2000 |
This publication is a compilation of some 1800 pages of outline drawings for microelectronic packages including transistors, diodes, DIPS, chip carriers and package interface BGA outlines in both inch and metric versions. Committee(s): JC-11 |
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3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions |
JEP158 | Nov 2009 |
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Free download. Registration or login required. |
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GUIDELINE FOR INTERNAL GAS ANALYSIS FOR MICROELECTRONIC PACKAGESStatus: Reaffirmed November 2020 |
JEP144A | Nov 2011 |
This guideline is applicable to hermetically sealed microelectronic components (including discrete semiconductors, monolithic and hybrid microcircuits). Specific cases with unique packaging, materials, or environmental constraints may not find all of the following information and procedures applicable. Committee(s): JC-13 Free download. Registration or login required. |
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POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA) |
JEP131C | Aug 2018 |
This publication applies to electronic components and subassemblies product and or process development, manufacturing processes and the associated performance requirements in customer applications. These areas should include, but are not limited to: package design, chip design, process development, assembly, fabrication, manufacturing, materials, quality, service, and suppliers, as well as the process requirements needed for the next assembly. Committee(s): JC-14.4 Free download. Registration or login required. |
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SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES |
JEP143D | Jan 2019 |
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Free download. Registration or login required. |
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LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES |
JEP160A | Aug 2022 |
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Free download. Registration or login required. |
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CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES |
JEP167A | Nov 2020 |
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required. |
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RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATIONStatus: Reaffirmed January 2024 |
JEP155B | Jul 2018 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history. Reaffirmed: January 2024 Free download. Registration or login required. |
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RECOMMENDED ESD-CDM TARGET LEVELS |
JEP157A | Apr 2022 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE |
JEP70C | Oct 2013 |
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. Committee(s): JC-14.4 Free download. Registration or login required. |
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RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENTStatus: Reaffirmed September 2019 |
JEP148B | Jan 2014 |
A concept is outlined, which proactively integrates qualification into the development process and provides a systematic procedure as support tool to development and gives early focus on required activities. It converts requirements for a product into measures of development and qualification in combination with a risk and opportunity assessment step and accompanies the development process as guiding and recording tool for advanced quality planning and confirmation. The collected data enlarge the knowledge database for DFR / BIR (design for reliability / building-in reliability) to be used for future projects. The procedure challenges and promotes teamwork of all involved disciplines. Free download. Registration or login required. |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites) |
JEP001-1A | Sep 2018 |
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required. |
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GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTSStatus: Reaffirmed May 2023 |
JEP142 | May 2023 |
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Free download. Registration or login required. |
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Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress |
JEP154A | Mar 2024 |
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. Free download. Registration or login required. |
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CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION |
JEP156A | Mar 2018 |
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Free download. Registration or login required. |
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Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA) |
JEP170A | Jun 2024 |
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Free download. Registration or login required. |
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SOLID STATE PRODUCTS REGISTRATION LIST(ORDER FROM TYPE ADMINISTRATION OFFICE)Status: ReaffirmedNovember 2002 |
JEP64 | Jan 1986 |
This publication includes addenda from 1976 to August 1986. The purpose of this list is to determine release numbers (file numbers) for JEDEC Type Designations. (See page 6 for more information.) Committee(s): JCJEDC |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURESStatus: Reaffirmed September 2019 |
JEP153A | Mar 2014 |
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Free download. Registration or login required. |
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A PROCEDURE FOR EXECUTING SWEAT:Status: Reaffirmed October 2012, September 2018 |
JEP119A | Aug 2003 |
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required. |