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Title	Document #	Date
ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST	JESD22-A118B.01	May 2021
The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES	JESD260	Apr 2021
This document provides the requirements for an additional block called as Replay Protection Monotonic Counter. (RPMC) Replay Protection provides a building block towards providing additional security. This block requires modifications in both a Serial Flash device and Serial Flash Controller. The standard defines new commands for Replay Protected Monotonic Counter operations. A device that supports RPMC can support these new commands as defined in this standard. Committee(s): JC-42.4 Free download. Registration or login required.
SERIAL FLASH RESET SIGNALING PROTOCOL	JESD252.01	Apr 2021
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166D	Apr 2021
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS	JEP178	Apr 2021
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required.
Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).	DR-4.18A.01	Apr 2021
Item 11.2-965(E) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION	JEP184	Mar 2021
The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well. Committee(s): JC-70.2 Free download. Registration or login required.
FLIP CHIP TENSILE PULL	JESD22-B109C	Mar 2021
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required.
Registration - Shipping and Handling Tray for DDR5 DIMM, 50 pcs	CO-036A	Mar 2021
Designator: N/A Item: 11.2-991, Access STP Files for CO-036A Cross Reference: N/A Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 39 Pin Removable Memory, 1.00 mm Pitch Microelectronic Assembly	MO-347A	Mar 2021
Designator: PBMA-N32[39]_Ip0-R14p1x18p1Z1p65-R0p71x1p1 Item: 11.11-987, Access STP Files for MO-347A Cross Reference: N/A Patents(): Kioxia: 1705380 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS Release Number: 31	MCP3.12.1	Mar 2021
Item 142.01, 142.02.This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SYSTEM LEVEL ROWHAMMER MITIGATION	JEP301-1	Mar 2021
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required.
NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION	JEP300-1	Mar 2021
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required.
HIGH BANDWIDTH MEMORY (HBM) DRAM	JESD235D	Mar 2021
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L. Committee(s): JC-42.3C Available for purchase: $247.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)	JESD209-4-1A	Feb 2021
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart Paying JEDEC Members may login for free access.
Addendum No. 1 to JESD79-4, 3D STACKED DRAM	JESD79-4-1B	Feb 2021
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD	JESD250C	Feb 2021
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99E. Committee(s): JC-42.3C Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BC	Feb 2021
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0	JESD253	Feb 2021
This document specifies the enclosure form factor which can be used with various type of SSD devices: outline of the top and bottom enclosure, three screw holes to mount the enclosure on the system, and two clamping holes in the top enclosure to lock to the connector. Item 318.06. Committee(s): JC-64.8 Free download. Registration or login required.
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick	MO-193G	Feb 2021
Designator: PDSO-G#_I0P##-##... Item 11.11-990 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs	JEP183	Jan 2021
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5	PS-005A	Jan 2021
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DDR4 NVDIMM-P BUS PROTOCOL	JESD304-4.01	Jan 2021
This version is a minor editorial adding Annex B that was left out of the original publication October 2020.An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 Free download. Registration or login required.
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP180.01	Jan 2021
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required.
COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS	JESD243A	Jan 2021
This standard identifies the best commercial practices for mitigating and/or avoiding counterfeit products by all manufacturers of electronic parts including, but not limited to original component manufacturers (OCMs), authorized aftermarket manufacturers, and other companies that manufacture electronic parts under their own logo, name, or trademark. The types of product this standard applies to is limited to monolithic microcircuits, hybrid microcircuits and discrete semiconductor products. Committee(s): JC-13 Free download. Registration or login required.
APPLICATION THERMAL DERATING METHODOLOGIES:	JEP149.01	Jan 2021
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
TEST METHOD FOR CONTINUOUS-SWITCHING EVALUATION OF GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP182	Jan 2021
This document is intended for use in the GaN power semiconductor and related power electronic industries and provides guidelines for test methods and circuits to be used for continuous-switching tests of GaN power conversion devices. Committee(s): JC-70.1 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package	MO-210Q	Jan 2021
Designator: PBGA-B#[#]_I0p... Item: 11.11-988, Access STP Files for MO-210Q Cross Reference: DG4.5 Patents(): May apply: Micron: 6,048,753. Tessera: 5,950,304; and 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS This is an editorial revision, details can be found in Annex F.	JEP162A.01	Jan 2021
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST	JESD22-A101D.01	Jan 2021
This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Registration - Plastic Bottom Grid Array Ball, 0.80 mm Pitch Square Family Package	MO-216G	Jan 2021
Designator: PBGA-B#[#]_I80... Item: 11.11-989, Access STP File for MO-216G Cross Reference: DR4.5 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch, Rectangular Family Package	MO-276P	Jan 2021
Designator: PBGA-B#[#]_I0p5... Item: 11.11-986, Access STP File for MO-276P Cross Reference: DR4.5 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)	JESD49B	Dec 2020
This standard was created to facilitate the procurement and use of high reliability semiconductor microcircuits or discrete devices provided in bare die form, commonly known as Known Good Die (KGD). Committee(s): JC-13 Free download. Registration or login required.
REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION:	JEP121B	Dec 2020
The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufacturer in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.D	Dec 2020
This specification defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.23 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex A, Raw Card A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.A	Dec 2020
Item No. 2204.22 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30A	MODULE4.20.26.B	Dec 2020
This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.26. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30	MODULE4.20.26.D	Dec 2020
This document defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.21A. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.E	Dec 2020
This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2232.20. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex B, Raw Card B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.B	Dec 2020
This specification defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.24. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30A	MODULE4.20.26.A	Nov 2020
This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2231.38A. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package	TO-220L.01	Nov 2020
Item 11.10-456(E) Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 6 Release Number: 30	SPD4.1.2.L-6	Nov 2020
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package	MO-346A	Nov 2020
Designator: PQFP-B#[#]_I0p65... Item: 11.11-981, Access STP Files for MO-346A Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0	JESD220-2B	Nov 2020
This standard specifies the characteristics of the UFS card electrical interface and the memory device. This document defines the added/modified features in UFS card compared to embedded UFS device. For other common features JESD220, UFS, will be referenced. Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-64.1 Available for purchase: $76.00 Add to Cart Paying JEDEC Members may login for free access.
TEMPERATURE CYCLING	JESD22-A104F	Nov 2020
This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses. Committee(s): JC-14.1 Free download. Registration or login required.
CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST	JESD22-A100E	Nov 2020
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES	JEP167A	Nov 2020
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required.
DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD	JESD404-1	Nov 2020
Definition for all DDRx component documents to reference. This is generic to any DDRxtechnology. Item 1842.34 Committee(s): JC-42.3C Free download. Registration or login required.
Standard - Plastic Dual Small Outline, 1.27 mm pitch, 7.50 mm Body Width Rectangular Package Family	MS-013G	Oct 2020
Designator: PDSO-G#-I1p27... Item 11.11-967(S). Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC MODULE SIDEBAND BUS (SidebandBus)	JESD403-1	Oct 2020
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C. Committee(s): JC-45 Free download. Registration or login required.
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick	MO-345A	Oct 2020
Designator: PDSO-G#_I0P5-##... Item: 11.11-984, Access STP Files for MO-345A Cross Reference: SO-023, GS-010C Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC Manual of Organization and Procedure	JM21T	Oct 2020
The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process. Committee(s): JC-BOD Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 2.0	JESD220-3A	Sep 2020
This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34 Patents(): WD: 9,323,657 Committee(s): JC-64.1 Available for purchase: $80.00 Add to Cart Paying JEDEC Members may login for free access.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements	JEP181	Sep 2020
This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Get the XML Schema: JEP181_Schema_R1p0. Committee(s): JC-15 Free download. Registration or login required.
Standard - Plastic Dual Small Outline (SO) Gull Wing, 1.27 mm Pitch Package	MS-012G.02	Sep 2020
Designator: PDSO-G#_I127-##... Item 11.11-972(E), Minor editorial correction. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 12 Pin UFS Card, 0.91 mm Pitch	MO-320B	Sep 2020
Designator: PBMA-N11-I0p91-CturZ1p0 Item 11.11-985 Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Dual Small Outline Gull Wing Package, 1.45 mm Thick	MO-178D	Sep 2020
Item 11.10-458 Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE	SO-023C	Sep 2020
Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2 Item: 11.14-202, Access STP Files for SO-023C Cross Reference: MO-329, GS-010C Patents(): CN 202759077 U Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly	MO-329C	Sep 2020
Designator: PDMA-N288-I0p85-R133p8x... Item: 11.14-201, Access STP Files for MO-329C Cross Reference: SO-023, GS-010C Patents(): Micron: 7,547,213. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.

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ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST

REPLAY PROTECTED MONOTONIC COUNTER (RPMC) FOR SERIAL FLASH DEVICES

SERIAL FLASH RESET SIGNALING PROTOCOL

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS

Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).

GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION

FLIP CHIP TENSILE PULL

Registration - Shipping and Handling Tray for DDR5 DIMM, 50 pcs

Registration - 39 Pin Removable Memory, 1.00 mm Pitch Microelectronic Assembly

Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

SYSTEM LEVEL ROWHAMMER MITIGATION

NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION

HIGH BANDWIDTH MEMORY (HBM) DRAM

ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X)

Addendum No. 1 to JESD79-4, 3D STACKED DRAM

GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD

STANDARD MANUFACTURERS IDENTIFICATION CODE

ENCLOSURE FORM FACTOR FOR SSD DEVICES, VERSION 1.0

Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick

Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

DDR5 288 Pin U/R/LR DIMM Connector Performance Standard, DDR5

DDR4 NVDIMM-P BUS PROTOCOL

GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

COUNTERFEIT ELECTRONIC PARTS: NON-PROLIFERATION FOR MANUFACTURERS

APPLICATION THERMAL DERATING METHODOLOGIES:

TEST METHOD FOR CONTINUOUS-SWITCHING EVALUATION OF GALLIUM NITRIDE POWER CONVERSION DEVICES

Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST

Registration - Plastic Bottom Grid Array Ball, 0.80 mm Pitch Square Family Package

Registration - Plastic Bottom Grid, Array Ball, 0.50 mm Pitch, Rectangular Family Package

PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)

REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION:

Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification

Annex A, Raw Card A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification

Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification

Annex B, Raw Card B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification

Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 6

Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package

UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0

TEMPERATURE CYCLING

CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST

CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES

DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD

Standard - Plastic Dual Small Outline, 1.27 mm pitch, 7.50 mm Body Width Rectangular Package Family

JEDEC MODULE SIDEBAND BUS (SidebandBus)

Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick

JEDEC Manual of Organization and Procedure

UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 2.0

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements

Standard - Plastic Dual Small Outline (SO) Gull Wing, 1.27 mm Pitch Package

Registration - 12 Pin UFS Card, 0.91 mm Pitch

Registration - Plastic Dual Small Outline Gull Wing Package, 1.45 mm Thick

REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE

Registration - 288 Pin DDR5 DIMM, 0.85 mm Pitch Microelectronic Assembly

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