Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package |
MO-340A | Oct 2019 |
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Quad Flatpack, 8 Terminal, 1.27 mm Pitch Package |
MO-341A | Oct 2019 |
Designator: PQFP-F8[10]_I127-R5p51x6.54Z1P1 Committee(s): JC-11.11 Free download. Registration or login required. |
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STANDARD MANUFACTURERS IDENTIFICATION CODENOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded. |
JEP106BA | Oct 2019 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS |
JEP162A | Sep 2019 |
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.80 MM x 0.70 MM Pitch Rectangular Family Package |
MO-338A | Sep 2019 |
Item 11.11-973, Access STP Files for MO-338A Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Bottom Flatpack 28 Terminal Package |
MO-339A | Sep 2019 |
Item 11-11.975, STP File for MO-339A Committee(s): JC-11.11 Free download. Registration or login required. |
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DESCRIPTIVE DESIGNATION SYSTEM FOR ELECTRONIC-DEVICE PACKAGES |
JESD30I | Aug 2019 |
This standard establishes requirements for the generation of electronic-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as uniform a manner as practicable. Item 11.2-962. Committee(s): JC-11.2 Free download. Registration or login required. |
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SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 5Release Number: 29 |
SPD4.1.2.L-5 | Aug 2019 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 5. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2276.05. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex L, Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 4Release Number: 27A |
SPD4.1.2.L-4 | Aug 2019 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 4. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01G. This is an editorial revision to the publication in January 2017. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 29 |
MODULE4.20.25 | Aug 2019 |
This document defines the electrical and mechanical requirements for 260 pin, 1.2 V (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops and other systems. This document also contains the DDR4 DIMM Label, Ranks Definition. Item 2224.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.26 | Aug 2019 |
This specification defines the electrical and mechanical requirements for the 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs are intended for use as main memory when installed in PCs. Item 2241.13A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP) |
JESD216D.01 | Aug 2019 |
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. Any company may request a Function Specific ID by making a request to the JEDEC office at juliec@jedec.org. Please include “Function Specific ID Request, JESD216” in the email subject line. Item 1775.15 and 1775.18. Committee(s): JC-42.4 Free download. Registration or login required. |
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DDR4 DIMM Product Label, Hybrid, Pre-Production, DDR4ERelease Number: 29 |
DIMM-LABEL4.19.4 | Aug 2019 |
This section covers DDR4 and DDR4E in both DRAM-only module types and Hybrid module types, as well as pre-production modules of both types. Item 2224.13A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR4 REGISTERING CLOCK DRIVER (DDR4RCD02) |
JESD82-31A | Aug 2019 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR4 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR4 RDIMM and LRDIMM applications. Any TBDs as of this document, are under discussion by the formulating committee. Item 314.08F. *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR4 DATA BUFFER DEFINITION (DDR4DB02) |
JESD82-32A | Aug 2019 |
This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D *If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-40.4 Free download. Registration or login required. |
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DDR5 DIMM SMT 288 PIN SOCKET OUTLINE 0.85 MM PITCH SKT |
SO-023B | Jul 2019 |
Item 11.14-196 Committee(s): JC-11.14 Free download. Registration or login required. |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP) |
JESD51-4A | Jul 2019 |
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required. |
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0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05) |
JESD8-33 | Jun 2019 |
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 159.03 Committee(s): JC-16 Free download. Registration or login required. |
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POD125 - 1.25 V PSEUDO OPEN DRAIN I/O |
JESD8-30A | Jun 2019 |
This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required. |
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NAND FLASH INTERFACE INTEROPERABILITY |
JESD230D | Jun 2019 |
This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. Item 1765.00 Committee(s): JC-42.4 Free download. Registration or login required. |
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POD135 - 1.35 V PSEUDO OPEN DRAIN I/O |
JESD8-21C | Jun 2019 |
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required. |
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MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY |
JESD22-B110B.01 | Jun 2019 |
Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104. Free download. Registration or login required. |
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288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.28 | May 2019 |
This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.05E Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - Silicon Bottom Grid Array Column, 0.048 x 0.0275 Pitch, Rectangular Family Package |
MO-316B | Apr 2019 |
Package Designator: SBGA-M#(#)_I0p055 Item Number: 11.4-966 Committee(s): JC-11.4 Free download. Registration or login required. |
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Annex K, Raw Card K, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 29 |
MODULE4.20.25.K.01 | Apr 2019 |
This specification defines the electrical and mechanical requirements for Raw Card K, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.59A Editorial. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Standard - Plastic Dual Small Outline (SO) Family, Gull Wing, 1.27 mm Pitch Package. PDSO-G. |
MS-012G.01 | Apr 2019 |
Item 11.11-972(E). Free download. Registration or login required. |
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Registration - 262 Pin DDR5 SODIMM, 0.50 mm Pitch Socket |
SO-024A | Apr 2019 |
Item 14-193 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - 262 Pin SODIMM, 0.50 mm Pitch Package |
MO-337A | Apr 2019 |
Item 14-192 Committee(s): JC-11.14 Free download. Registration or login required. |
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Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.28.B | Mar 2019 |
This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.50. Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex C, R/C C, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.28.C | Mar 2019 |
This document defines the electrical and mechanical requirements for Raw Card C, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.49. Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex E, R/C E, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design SpecificationRelease Number: 29 |
MODULE4.20.28.E | Mar 2019 |
This specification defines the electrical and mechanical requirements for Raw Card E, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.46 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 2928 |
MODULE4.20.26.A | Feb 2019 |
This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.38. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 5 (LPDDR5) |
JESD209-5 | Feb 2019 |
This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item 1854.99 Committee(s): JC-42.6 Available for purchase: $355.00 Add to Cart Paying JEDEC Members may login for free access. |
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Design Requirements - Ball Grid Array Package (BGA) |
DR-4.14J.01 | Feb 2019 |
Item 11.2-948E Committee(s): JC-11.2 Free download. Registration or login required. |
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DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES FOR GaN HEMT BASED POWER CONVERSION DEVICES, VERSION 1.0 |
JEP173 | Jan 2019 |
This document is intended for use in the GaN power semiconductor and related power electronic industries, and provides guidelines for measuring the dynamic ON-resistance of GaN power devices. Committee(s): JC-70.1 Free download. Registration or login required. |
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EMBEDDED MULTI-MEDIA CARD (e•MMC), ELECTRICAL STANDARD (5.1) |
JESD84-B51A | Jan 2019 |
This document provides a comprehensive definition of the e•MMC Electrical Interface, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. The purpose of this standard is the definition of the e•MMC Electrical Interface, its environment and handling. It provides guidelines for systems designers. Item 67.14. This document replaces all past versions, however links to the replaced versions are provided here for reference only: JESD84-B51, February 2015; JESD84-B50.1, July 2014 (Editorial revision of JESD84-B50); JESD84-B50, September 2013 (Revision of JESD84-B451); JESD84-B451, June 2012 (Revision of JESD84-B45, June 2011) Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-64 Available for purchase: $327.00 Add to Cart Paying JEDEC Members may login for free access. |
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SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES |
JEP143D | Jan 2019 |
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Free download. Registration or login required. |
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ANSI/ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2018 | Jan 2019 |
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package |
TO-220L | Jan 2019 |
Item 11.10-457 Free download. Registration or login required. |
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Annex A: Differences between JESD21C Release 28 and its predecessor JESD21C, Release 27.Release Number: 28 |
AnnexA - JESD21C | Jan 2019 |
This table briefly describes the changes made to this standard, JESD21-C, Release 28, compared to its predecessor, JESD21C, Release 27. Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING |
JEP118A | Dec 2018 |
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required. |
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DDR3 DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19.3 | Dec 2018 |
This section covers DDR3 DIMM labels. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19.2 | Dec 2018 |
This section covers DDR2 DIMM labels. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR DIMM Product LabelRelease Number: 28 |
DIMM-LABEL4.19-1 | Dec 2018 |
Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE 6 (GDDR6) SGRAM STANDARD |
JESD250B | Nov 2018 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Item 1836.99D. Committee(s): JC-42.3C Free download. Registration or login required. |
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HIGH BANDWIDTH MEMORY (HBM) DRAM |
JESD235B | Nov 2018 |
The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet. Item 1797.99J. Committee(s): JC-42.3C Available for purchase: $228.00 Add to Cart Paying JEDEC Members may login for free access. |
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ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM) PROGRAM/ERASE ENDURANCE AND DATA RETENTION TEST |
JESD22-A117E | Nov 2018 |
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94. Committee(s): JC-14.1 Free download. Registration or login required. |
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Annex B, R/C B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 28 |
MODULE4.20.26.B | Nov 2018 |
This document defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.29. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 28 |
MODULE4.20.26.D | Nov 2018 |
This document defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.37. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex A, R/C A, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 28 |
MODULE4.20.25.A | Nov 2018 |
This document defines the electrical and mechanical requirements for Raw Card A, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item 2228.63. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA) |
DR-4.5N.01 | Nov 2018 |
Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change. Committee(s): JC-11.2 Free download. Registration or login required. |
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Design Requirements - Ball Grid Array Package (BGA) |
DR-4.27F.01 | Nov 2018 |
Ball Pitch = 0.65, 0.75 and 0.80 mm, Body sizes >21mm. (For body sizes ≤ 21mm see Design Registration 4.5) Item 11.2-969E. Editorial Change Committee(s): JC-11.2 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array, Ball 0.70 mm Pitch, Square Family |
MO-336A | Nov 2018 |
Item 11-11.963 STP File for MO-336A Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.80 mm Pitch Square Family Package |
MO-216F | Nov 2018 |
PBGA-B#(#)_I80...Item 11-961 Committee(s): JC-11.11 Free download. Registration or login required. |
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Labeling Requirements for DDR Series DIMMsRelease Number: 28 |
DIMM-LABEL4.19 | Oct 2018 |
This standard provides the labels for the DDR Series DIMMs. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SERIAL FLASH RESET SIGNALING PROTOCOL |
JESD252 | Oct 2018 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06. Committee(s): JC-42.4 Free download. Registration or login required. |
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MECHANICAL COMPRESSIVE STATIC STRESS TEST METHOD |
JESD22-B119 | Oct 2018 |
This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress. Committee(s): JC-14.1 Free download. Registration or login required. |
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Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE |
JESD251-1 | Oct 2018 |
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. Committee(s): JC-42.4 Free download. Registration or login required. |
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COMPONENT QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS (INCLUDING ADMINISTRATIVE QUALITY PROBLEMS) |
JESD671D | Oct 2018 |
This revision now encompasses administrative quality problems, in addition to the electrical and visual/mechanical quality problems that were addressed in the original release. A standard set of problem categories for each of these three types of component problems is presented for tracking and reporting purposes. A common set of customer and supplier expectations and requirements are set forth to help facilitate the successful problem analysis and corrective action of any type of component quality problem. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999. Committee(s): JC-14.4 Free download. Registration or login required. |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites) |
JEP001-3A | Sep 2018 |
This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required. |