Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHESStatus: ReaffirmedApril 2023 |
JEP161 | Jan 2011 |
This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases. Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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UNDERSTANDING ELECTRICAL OVERSTRESS - EOSStatus: Reaffirmed May 2022 |
JEP174 | Sep 2016 |
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required. |
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Universal Flash Storage (UFS)Release Number: Version 4.1 |
JESD220G | Dec 2024 |
This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes. This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device. Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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Universal Flash Storage (UFS), Version 2.1Status: Superseded August 2020 |
JESD220C-2.1 | Mar 2016 |
This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model is referencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10 (SCSI) SPC and SBC standards. Item 133.00B Committee(s): JC-64.1 Free download. Registration or login required. |