Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD):Status: ReaffirmedOctober 2002 |
JESD24- 4 | Nov 1990 |
The purpose of this test method is to measure the thermal impedance of the Bipolar Transistor under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the base-emitter voltage is used as the junction temperature indicator. This test method is used to measure the thermal response of the junction to a heating pulse. Specifically, the test may be used to measure dc thermal resistance, and to ensure proper die mountdown to its case. This is accomplished through the appropriate choice of pulse duration and heating power magnitude. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-4 | Nov 1993 |
This Addendum No. 4 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices that can be a super-set of LVCMOS and LVTTL. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES: |
JESD12-5 | Aug 1988 |
This standard is intended to provide circuit designers with the information needed to develop complex integrated circuits that can be reliably and economically tested without compromising flexibility. Committee(s): JC-44 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD:Status: Reaffirmedoctober 2002 |
JESD24- 5 | Aug 1990 |
This method describes a means for testing the ability of a power switching device to withstand avalanche breakdown. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT |
JESD8-5A.01 | Sep 2007 |
This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for CMOS-compatible circuits. Committee(s): JC-16 Free download. Registration or login required. |
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