Standards & Documents Search

Displaying 116 - 120 of 1463 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES	JESD203	Nov 2005
This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to th publication of this document. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
STANDARD TEST AND PROGRAMMING LANGUAGE (STAPL):	JESD71	Aug 1999
STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices. Committee(s): JC-42.1 Free download. Registration or login required.
Standard Template for JEDEC Module Standards	MODULE4.20.1	Oct 2001
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES:	JESD13-B	May 1980
This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required.
Standard Practices and Procedures - Use of -PROPOSED- on Ballots.	SPP-007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.

Pages