Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed 04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required. |
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STANDARD TEST PROCEDURE FOR NOISE MARGIN MEASUREMENTS FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSStatus: Rescinded, October 2008 |
JESD390A | Feb 1981 |
Reaffirmed September 2003 Free download. Registration or login required. |
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STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) - LEAD (Pb) CONTENTReaffirmed June 2023 |
JESD213A | Apr 2017 |
This document is intended to be used by Original Component Manufacturers who deliver electronic components and Original Equipment Manufacturers who are the platform system integrators. It is intended to be applied prior to delivery by the OCMs and may be used by OEM system engineers and procuring activities as well as U.S Government Department of Defense system engineers, procuring activities and repair centers. This Standard establishes the instrumentation, techniques, criteria, and methods to be utilized to quantify the amount of Lead (Pb) in Tin-Lead (Sn/Pb) alloys and electroplated finishes containing at least 3 weight percent (wt%) Lead (Pb) using X-Ray Fluorescence (XRF) equipment. Reaffirmed June 2023
Committee(s): JC-13 Free download. Registration or login required. |
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STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES |
JESD203 | Nov 2005 |
This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to th Free download. Registration or login required. |
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STANDARD TEST AND PROGRAMMING LANGUAGE (STAPL): |
JESD71 | Aug 1999 |
STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices. Committee(s): JC-42.1 Free download. Registration or login required. |
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