Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERSStatus: Reaffirmed November 1999, May 2003 |
JEP103A | Jul 1996 |
In order to improve understanding between manufacturers and users, a consistent set of product-documentation classifications associated with the stages of product development. Committee(s): JC-10 Free download. Registration or login required. |
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Style Manual for Standards and Other Publications of JEDEC |
JM7A | Jul 2024 |
This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association. Committee(s): JC-10 Free download. Registration or login required. |
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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): |
JESD8-15A | Sep 2003 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. Committee(s): JC-16 Free download. Registration or login required. |
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS |
JESD47L | Dec 2022 |
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Available for purchase: $87.38 Add to Cart Paying JEDEC Members may login for free access. |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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