Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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DEVICE QUALITY PROBLEM ANALYSIS AND CORRECTIVE ACTION RESOLUTION METHODOLOGY |
JESD671D | Oct 2018 |
This standard addresses any Customer-initiated device problem analysis/corrective action request and Supplier/Authorized Distributor-identified device nonconformance to specification which may impact the Customer. This standard establishes a common set of Customer, Authorized Distributor and Supplier expectations and requirements that will help to facilitate successful problem analysis and corrective action of device problems, including administrative quality problems, which may affect the Customer. Formerly known as EIA-671 (November 1996). Became JESD671-A after revision, December 1999. Committee(s): JC-14.4 Free download. Registration or login required. |
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Device Specification Annex for JESD21-C |
SDRAM3.2 | Apr 2003 |
Release No.12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 7th Edition |
JESD88G | Mar 2025 |
This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry Committee(s): JC-10 Free download. Registration or login required. |
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DIGITAL BIPOLAR LOGIC PINOUTS FOR CHIP CARRIERS: |
JESD2 | Dec 1982 |
This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices. Committee(s): JC-40.1 Free download. Registration or login required. |
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DIMM Design Files |
DIMM Homepage | Dec 2003 |
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. |
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