Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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ADDENDUM No. 6 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS:Status: ReaffirmedOctober 2002 |
JESD24- 6 | Oct 1991 |
This standard describes in detail the method for thermal measurements of Insulated Gate Bipolar Transistors (IGBTs) and is suitable for use both in manufacturing and application of the devices. The method covers both thermal transient and thermal equilibrium measurements for manufacturing process control and device characterization purposes. Properly implemented, JESD24-6 provides a basis for obtaining realistic thermal parametric values that will benefit supplier's internal effectiveness and will be useful to the design and manufacturer of reliable IGBT circuits. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-6 | Aug 1995 |
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 7 to JESD24 - COMMUTATING DIODE SAFE OPERATING AREA TEST PROCEDURE FOR MEASURING dv/dt DURING REVERSE RECOVERY OF POWER TRANSISTORS:Status: ReaffirmedOctober 2002 |
JESD24- 7 | Aug 1982 |
Defines methods for verifying the diode recovery stress capability of power transistors. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT: |
JESD8-7A | Jun 2006 |
This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established. Since this migration is driven by both process changes and performance/power, more entries can be expected in supporting required voltage levels. The rapidity of this evolution is expecting to increase because of the same feature sizes expected. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING:Status: ReaffirmedOctober 2002 |
JESD24- 8 | Aug 1992 |
Determines the repetitive inductive avalanche switching capability of power switching transistors. Committee(s): JC-25 Free download. Registration or login required. |
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