Standards & Documents Search

Displaying 116 - 120 of 1471 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)	JESD255	Mar 2024
The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress	JEP154A	Mar 2024
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices	JESD625C.01	Mar 2024
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-13, JC-14.1 Free download. Registration or login required.
DDR5 Clock Driver Definition (DDR5CKD01) Release Number: Version 1.1	JESD82-531A.01	Feb 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
SHIPPING AND HANDLING TRAY FOR DDR5 SODIMM MICROELECTRONIC ASSEMBLY	CO-037A	Jan 2024
Designator: N/A Item #: 11.5-995 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.

Pages