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Title	Document #	Date
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL	JS-001-2024	Oct 2024
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230G	Oct 2024
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
DDR5 262 Pin SODIMM Connector Performance Standard	PS-006B	Sep 2024
This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE	JEP106BK	Sep 2024
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)	JESD239A	Sep 2024
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. Committee(s): JC-42, JC-42.1 Free download. Registration or login required.

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