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Title	Document #	Date
POWER AND TEMPERATURE CYCLING	JESD22-A105D	Jan 2020
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Low Power Double Data Rate 5 (LPDDR5)	JESD209-5A	Jan 2020
This document defines the LPDDR5 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant x16 one channel SDRAM device and x8 one channel SDRAM device. LPDDR5 device density ranges from 2 Gb through 32 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and LPDDR4 (JESD209-4). Item 1854.99A Committee(s): JC-42.6 Available for purchase: $369.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
UNIVERSAL FLASH STORAGE (UFS), Version 3.1	JESD220E	Jan 2020
This document replaces all past versions, however JESD220D, January (V 3.0), is available for reference only.The purpose of this standard is definition of an UFS Universal Flash Storage electrical interface and an UFS memory device. This standard defines a unique UFS feature set and includes the feature set of e·MMC Specification as a subset. This standard references also several other standard specifications by MIPI (M-PHY and UniPro Specifications) and INCITS T10 (SBC, SPC and SAM Standards) organizations. For more information about how to access and download the MIPI specifications related to UFS, visit: https://www.mipi.org/mipi-jedec/DocumentRequestWelcome. Item 135.99 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-64.1 Available for purchase: $355.00 Add to Cart Paying JEDEC Members may login for free access.
MARK LEGIBILITY	JESD22-B114B	Jan 2020
This standard describes a nondestructive test to assess solid state device mark legibility. The specification applies only to solid state devices that contain markings, regardless of the marking method. It does not define what devices must be marked or the method in which the device is marked, i.e., ink, laser, etc. The standard is limited in scope to the legibility requirements of solid state devices, and does not replace related reference documents listed in this standard. Committee(s): JC-14.1 Free download. Registration or login required.
Registration - Plastic Dual Small Outline Surface Terminal, Wettable Flank Package	MO-340A	Oct 2019
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Item: 11.11-974, Access STP Files for MO-340A Cross Reference: DR4.8, DR4.16, DR4.20 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.

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