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This Unified Memory Extension standard is an extension to the UFSHCI standard, JESD223. The UFSHCI standard defines the interface between the UFS driver and the UFS host controller. In addition to the register interface, it defines data structures inside the system memory, which are used to exchange data, control and status information. Furthermore the UFSHCI standard defines the protocol layer structure and abstract entities within these layers. Unified Memory offers the possibility to move Device internal working memory into the system memory to reduce overall system cost and to improve Device performance. Item 203.25

Patents(): Apple: 2010/0250836; Toshiba: P2011-252001, 13/561392, 101126675, 201210272624.X, 13/758090, 101132071, 201210332970.2, P2012-194380, P2012-194380, P2012-194380; Memory Technology: 2013/0198434, 2010/0312947

Committee(s): JC-64.1

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This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes.

This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device.

Committee(s): JC-64, JC-64.1

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This document provides a comprehensive definition of the UFS security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead.

Committee(s): JC-64.1

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This document has been superseded by JESD220F, August 2022, however is available for reference only.

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Committee(s): JC-64.1

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This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34

Patents(): WD: 9,323,657

Committee(s): JC-64.1

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This document replaces all prior versions; however, JESD223E August 2022 (version 4.0) remains available for reference purposes.

This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY].

Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI.

Committee(s): JC-64, JC-64.1

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This standard specifies the mechanical and electrical characteristics of the XFM removable memory Device.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64, JC-64.1

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NOTE: This document has been superseded by JESD220G published in December 2024, but remains available for reference purposes.

Committee(s): JC-64.1

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This document provides a definition of the Embedded MultiMediaCard product, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in costs.

Committee(s): JC-64, JC-64.1

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2

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This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level.

Committee(s): JC-14, JC-14.3

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Release No. 14

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

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This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the “Design Kit” subsection of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2

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