Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # | Date |
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GUIDELINES FOR REPORTING AND USING ELECTRONIC PACKAGE THERMAL INFORMATION |
JESD51-12.01 | Nov 2012 |
This document provides guidelines for both reporting and using electronic package thermal information generated using JEDEC JESD51 standards. By addressing these two areas, this document can be used as the common basis for discussion between electronic package thermal information suppliers and users. Free download. Registration or login required. |
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IMPLEMENTATION OF THE ELECTRICAL TEST METHOD FOR THE MEASUREMENT OF REAL THERMAL RESISTANCE AND IMPEDANCE OF LIGHT-EMITTING DIODES WITH EXPOSED COOLING SURFACE |
JESD51-51A | Nov 2022 |
The purpose of this document is to specify, how LEDs thermal metrics and other thermally-related data are best identified by physical measurements using well established testing procedures defined for thermal testing of packaged semiconductor devices (published and maintained by JEDEC) and defined for characterization of light sources (published and maintained by CIE – the International Commission on Illumination). Committee(s): JC-15 Free download. Registration or login required. |
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THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES |
JESD51-31 | Jul 2008 |
This document specifies the appropriate modifications needed for Multi-Chip Packages to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this document are the raw data used to document the thermal performance of the package. The use of this data will be documented in JESD51-XX, Guideline to Support Effective Use of MCP Thermal Measurements which is being prepared. Committee(s): JC-15 Free download. Registration or login required. |
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INTEGRATED CIRCUITS THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - NATURAL CONVECTION (STILL AIR) |
JESD51-2A | Jan 2007 |
This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection. Committee(s): JC-15.1 Free download. Registration or login required. |
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TERMS, DEFINITIONS AND UNITS GLOSSARY FOR LED THERMAL TESTING |
JESD51-53A | Oct 2022 |
This document provides a unified collection of the commonly used terms and definitions in the area of LED thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents, especially in JESD51-13, in order to include other often used terms and definitions in the area of light output measurements of LEDs. Definitions, symbols and notations regarding light output measurements used here are consistent with those defined in JESD77C.01 and with those defined by CIE (International Commission on Illumination), especially in the International Lighting Vocabulary, CIE S 017/E:2011 ILV and in the CIE 127-2007 document as well as in some other relevant standards of other standardization bodies from the solid-state lighting industry, e.g., ANSI/IESNA RP 16-05. Committee(s): JC-15 Free download. Registration or login required. |
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GUIDELINES FOR COMBINING CIE 127-2007 TOTAL FLUX MEASUREMENTS WITH THERMAL MEASUREMENTS OF LEDS WITH EXPOSED COOLING SURFACE |
JESD51-52A | Nov 2022 |
This document is intended to be used in conjunction with the JESD51-50 series of standards, especially with JESD51-51 (Implementation of the Electrical Test Method for the Measurement of Real Thermal Resistance and Impedance of Light-emitting Diodes with Exposed Cooling Surface) document. This present document focuses on the measurement of the total radiant flux of LEDs in combination with the measurement of LEDs's thermal characteristics: guidelines on the implementation of the recommendations of the CIE 127-2007 document are provided. Committee(s): JC-15 Free download. Registration or login required. |
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TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE |
JESD15-3 | Jul 2008 |
This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from the JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this document is limited to single-die packages that can be effectively represented by a single junction temperature. Committee(s): JC-15 Free download. Registration or login required. |
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GLOSSARY OF THERMAL MEASUREMENT TERMS AND DEFINITIONS |
JESD51-13 | Jun 2009 |
This document provides a unified collection of the commonly used terms and definitions in the area of semiconductor thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 family of documents to include other often used terms and definitions in the area of semiconductor thermal measurements. Committee(s): JC-15 Free download. Registration or login required. |
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EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES |
JESD51-32 | Dec 2010 |
This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described in this standard are also applicable to single chip packages needing more than 36 electrical connections for the test. Committee(s): JC-15 Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - JUNCTION-TO-BOARD: |
JESD51- 8 | Oct 1999 |
This specification should be used in conjunction with the overview document JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) [1] and the electrical test procedures described in JESD51-1, 'Integrated Circuit Thermal Measurement Method (Single Semiconductor Device' [2. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paths to the printed board caused by such thermal enhancements as fused leads (leads connected to the die pad) or power style packages with the exposed heat slug on one side of the package. Committee(s): JC-15.1 Free download. Registration or login required. |
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TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS: |
JESD51-10 | Jul 2000 |
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Dual-Inline Packages (DIP) and Single-Inline Packages (SIP). It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-10 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required. |
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TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS: |
JESD51- 9 | Jul 2000 |
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of ball grid array (BGA) and land grid array (LGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-9 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR): |
JESD51- 6 | Mar 1999 |
This standard specifies the environmental conditions for determining thermal performance of an integrated circuit device in a forced convection environment when mounted on a standard thermal test board. Committee(s): JC-15.1 Free download. Registration or login required. |
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TRANSIENT DUAL INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW THROUGH A SINGLE PATH |
JESD51-14 | Nov 2010 |
This document specifies a test method (referred to herein as “Transient Dual Interface Measurement”) to determine the conductive thermal resistance “Junction-to-Case” RθJC (θJC) of semiconductor devices with a heat flow through a single path, i.e., semiconductor devices with a high conductive heat flow path from the die surface that is heated to a package case surface that can be cooled by contacting it to an external heat sink. TDIM Master Software: TDIM-Master-2011-04-06.zip
Committee(s): JC-15 Free download. Registration or login required. |
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DICTIONARY OF TERMS FOR SOLID-STATE TECHNOLOGY, 7th Edition |
JESD88G | Mar 2025 |
This reference for technical writers and educators, manufacturers, and buyers and users of discrete solid state devices is now available. It should aid the technical committees of JEDEC in the avoidance of multiple definitions and reduce the proliferation of redundant definitions. The long-term goal is to include definitions from all JEDEC publications and standards. Each of the approximately two thousand entries is referenced to its source publication, and an annex listing the names of the source publications and their releases dates is included. All entries were reviewed for punctuation, grammar, and clarity, as well as accuracy, and reworded if such was considered warranted. The purpose of this dictionary is to promote the uniform use of terms, definitions, abbreviations, and symbols throughout the solid state industry Committee(s): JC-10 Free download. Registration or login required. |
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Temperature Range and Measurement Standards for Components and Modules |
JESD402-1B | Sep 2024 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Committee(s): JC-42 Free download. Registration or login required. |
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EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS: |
JESD51- 5 | Feb 1999 |
This extension of the thermal standards provides a standard fixture for direct attach type packages such as deep-downset of thermally tabbed packages. This specification provides additional design detail for use in developing thermal test boards with application to these package types. This document is in addition to and not replacement for the design specifications in other standards. Committee(s): JC-15.1 Free download. Registration or login required. |
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TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT: |
JESD51-11 | Jun 2001 |
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Pin Grid Array (PGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-11 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required. |
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Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements |
JEP30-T100B.01 | Feb 2025 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-15 Free download. Registration or login required. |
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DELPHI COMPACT THERMAL MODEL GUIDELINE |
JESD15-4 | Oct 2008 |
This guideline specifies the definition and lists acceptable approaches for constructing a compact thermal model (CTM) based on the DELPHI methodology. The purpose of this document is twofold. First, it aims to provide clear guidance to those seeking to create DELPHI compact models of packages. Second, it aims to provide users with an understanding of the methodology by which they are created and validated, and the issues associated with their use. Committee(s): JC-15 Free download. Registration or login required. |
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OVERVIEW OF METHODOLOGIES FOR THE THERMAL MEASUREMENT OF SINGLE- AND MULTI-CHIP, SINGLE- AND MULTI-PN-JUNCTION LIGHT-EMITTING DIODES (LEDS) |
JESD51-50A | Nov 2022 |
This document provides an overview of the methodology necessary for making meaningful thermal measurements on high-power light-emitting diodes (LEDs) built on single or multiple chips with one or more pn-junctions per chip. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15 Free download. Registration or login required. |
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SPD Annex J: Serial Presence Detect for DDR2 SDRAM |
SPD4.1.2.10 | Jan 2007 |
Release No. 17 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES: |
JESD51- 7 | Feb 1999 |
This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. The objective of the standard is to provide a high effective thermal conductivity mounting surface that can be compared equally against standard tests done in different laboratories with typical variations of less than or equal to 10%. Committee(s): JC-15.1 Free download. Registration or login required. |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP) |
JESD51-4A | Jul 2019 |
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required. |
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SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1 |
SPD4.1.2.7 | Jun 2006 |
Release No. 16A. Item 2003.02A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997.Status: ElevatedSeptember 1997 |
JEP129 | Feb 1997 |
Committee(s): JC-15.1 Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE): |
JESD51- 1 | Dec 1995 |
The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. This method will provide a basis for comparison of different devices housed in the same electronic package or similar devices housed in different electronic packages. Committee(s): JC-15.1 Free download. Registration or login required. |
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APPLICATION THERMAL DERATING METHODOLOGIES: |
JEP149.01 | Jan 2021 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |
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COMPACT THERMAL MODEL OVERVIEW |
JESD15-1.01 | Mar 2023 |
Terminology update. This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Free download. Registration or login required. |
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THERMAL MODELING OVERVIEW |
JESD15 | Oct 2008 |
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Free download. Registration or login required. |
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LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES: |
JESD51- 3 | Aug 1996 |
This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, trace thickness, and routing considerations. Application includes still air and moving air thermal tests. Committee(s): JC-15.1 Free download. Registration or login required. |
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METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE) |
JESD51 | Dec 1995 |
This standard and its subsequent addendum's, provides a standard for thermal measurement that, if followed fully, will provide correct and meaningful data that will allow for determination of junction temperature for specific conditions. The data can be used for package design evaluation, device characterization and reliability predictions. Free download. Registration or login required. |
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MECHANICAL SHOCK – DEVICE AND SUBASSEMBLY |
JESD22-B110B.01 | Jun 2019 |
Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104. Free download. Registration or login required. |
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Addendum No. 2 to JESD79-3, 1.25 V DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600 |
JESD79-3-2 | Oct 2011 |
The purpose of this addendum is to define the DDR3U specifications that supersede the DDR3 specifications in the JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, and DDR3-1600 titles in JESD79-3 are to be interpreted as DDR3U-800, DDR3U-1066, DDR3U-1333, and DDR3U-1600, respectively, when applying towards DDR3U definition; unless specifically stated otherwise. Item 1769.01 Committee(s): JC-42.3 Free download. Registration or login required. |
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Part Model Supply Chain Guidelines for Electronic-Device Packages – XML Requirements |
JEP30-S100A.02 | Feb 2025 |
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14.4 Free download. Registration or login required. |
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ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements |
JEP181A | Nov 2023 |
This publication establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. Committee(s): JC-15 Free download. Registration or login required. |
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DEFINITION OF THE SSTE32882 REGISTERING CLOCK DRIVER WITH PARITY AND QUAD CHIP SELECTS FOR DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V APPLICATIONS |
JESD82-29A.01 | Jan 2023 |
Terminology update. The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3, JC-40.4 Free download. Registration or login required. |
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SPECIALITY DDR2-1066 SDRAM |
JESD208 | Nov 2007 |
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required. |
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DDR2 SDRAM STANDARD |
JESD79-2F | Nov 2009 |
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Free download. Registration or login required. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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