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Item 2241.03B - Editorial

This specification defines the electrical and mechanical requirements for Raw Card H, 288-pin, 1.2 V (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs.

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Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Item 2241.16
This specification defines the electrical and mechanical requirements for Raw Card J, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Release No. 24. Item 2192.68

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Committee(s): JC-45.4

JESD21-C Solid State Memory Documents Main Page

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Release No. 22. Item 2145.38

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Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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This annex describes the serial presence detect (SPD) values for all LPDDR modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2254.02A

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Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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Release No. 22. Item 2145.35

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Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Release No. 19

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Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

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Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org.

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Committee(s): JC-11

The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments.

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Committee(s): JC-14.3

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This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation. Derivation of any new methods for combing groups for AOQ estimation. Derivation of any new methods introduced into this document have been provided in annexes. A statistical method is based on confidence interval statistics. A procedure was established for reporting AOQ when the minimum sample size criterion is not met. Not all sections of EIA-554 are appropriate for use by device manufacturers therefore JEDEC wishes to continue using JESD16. In December 2008 the formulating committee approved to remove EIA-554 (July 1996, Reaffirmed September 2002) from the JEDEC website. To obtain a copy of EIA-554 please contact GEIA at http://www.geia.org/

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Committee(s): JC-13

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This standard is applicable to avalanche breakdown diodes when used as a surge protector or transient voltage suppressor (TVS). It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. This standard may be applied to other surge-protection components with similar characteristics as the ABD.

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Committee(s): JC-22.2, JC-22.5

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This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and 3-bit logic devices.

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Committee(s): JC-40

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This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use.

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Committee(s): JC-40

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This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

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Committee(s): JC-40

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Release No. 9

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Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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Release No.9

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Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of surface mount electronic components in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of surface mounted components while duplicating the failure modes normally observed during product level test. This is not a component qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.

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Committee(s): JC-14, JC-14.1

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This standard describes the modeling of a bond wire from an integrated circuit (IC) die to a package lead in a ball or wedge type wire bond configuration.

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Committee(s): JC-15.2

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This standard specifies the host and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. This standard is used in conjunction with JESD248. Item 2233.54G

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Committee(s): JC-45.6

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