Standards & Documents Search

This document provides a comprehensive definition of the MultiMediaCard, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in costs.

Patents(): Samsung; Qimonda; Nokia

Committee(s): JC-64, JC-64.1

Free download. Registration or login required.

This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00

Patents(): Kandou

Committee(s): JC-16

Free download. Registration or login required.

Release No.9

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 11

Committee(s): JC-42.5

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Committee(s): JCJEDC

This standard establishes methods for calculating failure rates in units of FITs by using data in varying degrees of detail such that results can be obtained from almost any data set. The objective is to provide a reference to the way failure rates are calculated.

Committee(s): JC-14.3

Free download. Registration or login required.

This standard was updated and revised for the purpose of clarifying the method used to measure Q of a Voltage-Variable-Capacitance Diode in the low VHF range using an RF admittance bridge. Originally published November 1981. Approved as ANSI/EIA-381-A-1992, July 1992. Became JESD381-A after ANSI expiration July 2002.

Committee(s): JC-22.4

Free download. Registration or login required.

This is an accelerated stress test method for determining sample estimates and their confidence limits of the median-time-to-failure, sigma, and early percentile of a log-Normal distribution, which are used to characterize the electromigration failure-time distribution of equivalent metal lines subjected to a constant current-density and temperature stress. Failure is defined as some pre-selected fractional increase in the resistance of the line under test. Analysis procedures are provided to analyze complete and singly, right-censored failure-time data. Sample calculations for complete and right-censored data are provided in Annex A. The analyses are not intended for the case when the failure distribution cannot be characterized by a single log-Normal distribution.

Committee(s): JC-14, JC-14.2

Free download. Registration or login required.

Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress.

Committee(s): JC-14.1

Free download. Registration or login required.

This standard describes a test method for measurement of transistor noise figure and effective input noise temperature at MF, HF, and VHF. This standard also adds the necessary information to make 'effective input noise temperature measurements'. This method is a revision of EIA-311 and incorporates material previously found in EIA-283, Test Method for Transistor Noise Figure Measurements at Medium Frequencies, Rescinded November 1981. Formerly known as RS-311 and/or EIA-311-A.

Committee(s): JC-25

Free download. Registration or login required.

This standard provides a test method and definition for small-signal conditions at microwave frequencies.

Committee(s): JC-25

Free download. Registration or login required.

This standard gives a test method for measuring transistor capacitance using a three-terminal bridge which employs a guard-circuit that eliminates the effect of extraneous capacitance.

Committee(s): JC-25

Free download. Registration or login required.

This standard describes the measurement of signal diodes (IF <=500mA dc) reverse recovery times of less than 300 ns duration. It may, however, also be used for the measurement of longer recovery times. This standard is also intended to establish a method which to characterize the test fixture used for this measurement.

Committee(s): JC-22.4

Free download. Registration or login required.

This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER) testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and accelerated testing procedures are described. At terrestrial, Earth-based altitudes, the predominant sources of radiation include both cosmic-ray radiation and alpha-particle radiation from radioisotopic impurities in the package and chip materials. An overall assessment of a deviceís SER is complete, only when an unaccelerated test is done, or accelerated SER data for the alpha-particle component and the cosmic-radiation component has been obtained.

Committee(s): JC-13, JC-13.4

Free download. Registration or login required.

Item 142.12

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

Committee(s): JC-64.2

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This document has been worked on for more than three years by member companies of EICTA (Europe), JGPSSI (Japan), EIA (USA) and JEDEC (USA). The purpose of this guide establishes the materials and substances to be disclosed by suppliers when those materials and substances are present in products and subparts that are incorporated into EEE. It benefits suppliers and their commercial customers by providing consistency and efficiency to the material declaration process. It promotes the development of consistent data exchange formats and tools that will facilitate and improve data transfer along the entire global supply chain.

Committee(s): JC-CHM

Free download. Registration or login required.

This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes, and it describes the marking and labeling of their shipping containers to identify their 2nd  level terminal finish or material.

Committee(s): JC-14, JC-14.4

Free download. Registration or login required.

This test method provides two tests for determining the marking permanency of ink marked integrated circuits. A new non-destructive tape test method is introduced to quickly determine marking integrity. The test method also specifies a resistance to solvents method based upon MIL Std 883 Method 2015.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.