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Title	Document #	Date
TYPE DESIGNATION SYSTEM FOR MICROELECTRONIC DEVICES Status: Rescinded<p>September 1993</p>	EIA428-A	Jan 1988
Committee(s): JC-10
TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE	JESD15-3	Jul 2008
This document specifies the definition and construction of a two-resistor compact thermal model (CTM) from the JEDEC junction-to-case and junction-to-board thermal metrics. The guidance provided in this document only applies to thermal metrics defined in JEDEC standards JESD51-8 and JESD51-12. The scope of this document is limited to single-die packages that can be effectively represented by a single junction temperature. Committee(s): JC-15 Free download. Registration or login required.
Two Byte Modules Cards	MODULE4.3	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TSE2002 Serial Presence Detect with Thermal Sensor	PRN09-NV2	Jul 2009
Preliminary publication of BoD-approved ballot material, prior to its inclusion in the next release of the appropriate JEDEC Standard. Item 1756.00A Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TS511X, TS521X Serial Bus Thermal Sensor Device Standard	JESD302-1A	Aug 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for fifth generation Temperature Sensor (TS5) as used for memory module applications. These device operate on I2C and I3C two-wire serial bus interface. The designation TS521X and TS511X refers to the device specified by this document. Committee(s): JC-40.1 Free download. Registration or login required.
TS3000 Standalone Thermal Sensor Component	SPD4.1.5	Nov 2009
Release No. 19A, Item 1640.11 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION:	JES2	Jul 1992
Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft communications transmitters. Identifies the electrical parameters, wafer acceptance tests, screening tests, qualification tests, and lot acceptance tests pertinent to power GaAs FETs. Applicable to packaged and chip-carrier parts; portions may not be applicable to unpackaged and unmounted chips. Committee(s): JC-14.7 Free download. Registration or login required.
TRANSIENT VOLTAGE SUPPRESSOR STANDARD FOR THYRISTOR SURGE PROTECTIVE DEVICE: Status: ReaffirmedNovember 2006	JESD66	Nov 1999
This standard is applicable to Thyristor Surge Protective Devices. It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. The intended users of this standard are those interested in Thyristor Surge Protective Device characterization and rating verification. These devices are used primarily by the telecommunications industry to protect circuits from harmful overvoltages. The Thyristor Surge Protective Device (TSPD) is a semiconductor device that is finding widespread application in the telecommunication industry. The intent of this stand is to provide information on test methods that will reduce the possibility of disagreement and misunderstanding between TSPD vendors and users, and facilitate the determination of device interchangeability. Committee(s): JC-22.5 Free download. Registration or login required.
TRANSIENT DUAL INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW THROUGH A SINGLE PATH	JESD51-14	Nov 2010
This document specifies a test method (referred to herein as “Transient Dual Interface Measurement”) to determine the conductive thermal resistance “Junction-to-Case” RθJC (θJC) of semiconductor devices with a heat flow through a single path, i.e., semiconductor devices with a high conductive heat flow path from the die surface that is heated to a package case surface that can be cooled by contacting it to an external heat sink. TDIM Master Software: TDIM-Master-2011-04-06.zip Committee(s): JC-15 Free download. Registration or login required.
THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES	JESD51-31	Jul 2008
This document specifies the appropriate modifications needed for Multi-Chip Packages to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this document are the raw data used to document the thermal performance of the package. The use of this data will be documented in JESD51-XX, Guideline to Support Effective Use of MCP Thermal Measurements which is being prepared. Committee(s): JC-15 Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997. Status: ElevatedSeptember 1997	JEP129	Feb 1997
Committee(s): JC-15.1 Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)	JESD51-4A	Jul 2019
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD): Status: ReaffirmedApril 1999, April 2002	JESD531	Jul 1986
This standard describes a test method for measuring the thermal resistance of signal and regulator diodes. The need for modification of this test method arose out of the limited description that existed earlier for both signal and regulator diode applications in testing for thermal resistance. Previously published as ID-13. ANSI/EIA-531-1986 (July) expired June 1996. Became JESD531 after reaffirmation April 2002. Committee(s): JC-22.4 Free download. Registration or login required.
THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORS: Status: ReaffirmedApril 1981, April 2001	JESD313-B	Oct 1975
This standard provides a test method for measuring thermal resistance for conduction cooled power transistors. Committee(s): JC-25 Free download. Registration or login required.
THERMAL RESISTANCE FOR TEST METHODS FOR SIGNAL DIODES - SUPERSEDED BY EIA-531, July 1986. See JESD531, April 2002. Status: Rescinded	JEP90	Sep 1983
Committee(s): JC-22.4 Free download. Registration or login required.
THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORS Status: Rescinded	JEP88	Jan 1974
Committee(s): JC-22.1
THERMAL MODELING OVERVIEW	JESD15	Oct 2008
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)	JESD24-12	Jun 2004
The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate Bipolar Transistor) under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the collector-emitter on voltage, VCE(on), is used as the junction temperature indicator. This is an alternative method to JEDEC Standard No. 24-6. Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD Status: Reaffirmed April 1981, April 1999, March 2009	JESD353	Apr 1968
This noise measurement method applies to transistors whose noise has a Gaussian power distribution, to transistors whose noise has a flat (white) power distribution, and to transistors whose noise has a l/f (power inversely proportional to frequency) power distribution. Formerly known as RS-353 and/or EIA-353 Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF TRANSISTOR EQUIVALENT NOISE VOLTAGE AND EQUIVALENT NOISE CURRENT AT FREQUENCIES OF UP TO 20 kHz Status: Reaffirmed April 1981, April 1999, March 2009	JESD354	Apr 1968
This standard provides a method for determining values, for device registration purposes, for transistor equivalent noise voltage and equivalent noise current at frequencies up to 20 kHz. This method is applicable to transistors whose noise has a Gaussian, flat (white) or I/f power distribution. Formerly known as RS-354 and/or EIA-354 Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR SHORT-CIRCUIT FORWARD CURRENT TRANSFER RATIO: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD371	Feb 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor short-circuit forward current transfer ratio, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-371 and/or EIA-371. Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD372	May 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor admittance parameters, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-372 and/or EIA-372 Committee(s): JC-25 Free download. Registration or login required.
TEST TRACE FOR 64 GB - 128 GB SSD	JESD219A_TT	Jul 2012
The Test Trace file is a supporting file for implementation of the endurance verification client workload and is used in conjunction with JESD219A. This Test Trace is derived from the 128 GB Master Trace using the compression method described in JESD219 to enable testing on SSDs with a capacity range of 64 GB to 128 GB. All characteristics of this Test Trace are identical to the Master Trace except that the maximum LBA represents an SSD user capacity of 64 GB. Committee(s): JC-64.8 Free download. Registration or login required.
TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES	JESD234	Oct 2013
This test standard defines the requirements and procedures for 40 to 500 MeV proton irradiation of electronic devices for Single Event Effects (SEE), and reporting the results. Protons are capable of causing SEE by both direct and indirect ionization, however, in this energy range, indirect ionization will be the dominant cause of SEE [1-3]. Indirect ionization is produced from secondary particles of proton/material nuclear reactions, where the material is Si or any other element present in the semiconductor. Direct proton ionization is thought to be a minor source of SEE, at these energies. This energy range is also selected to coincide with the commonly used proton facilities, and result in the fewest energy dependent issues during test. Committee(s): JC-13, JC-13.4 Free download. Registration or login required.
TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS: Status: ReaffirmedSeptember 1981, April 1999	JEP65	Dec 1967
This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with formats developed for device registration and defining data. Committee(s): JC-25 Free download. Registration or login required.
TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C. Status: RescindedJun-96	JEP111	Jan 1986
Committee(s): JC-13, JC-13.2
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices	JEP151A	Jan 2022
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s): JC-14.1 Free download. Registration or login required.
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION:	JESD57A	Nov 2017
This test method defines requirements and procedures for ground simulation and single event effects (SEE) and implementation of the method in testing integrated circuits. This standard is valid when using a cyclotron or Van de Graaff accelerator. Microcircuits under test must be delidded. The ions used at the facilities have an atomic number Z > 2. It does not apply to SEE testing that uses protons, neutrons, or other lighter particles. This standard is designed to eliminate any misunderstanding between users of the method and test facilities, to minimize delays, and to promote standardization of testing and test data. Committee(s): JC-13.4 Free download. Registration or login required.
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES	JESD217A.01	Nov 2022
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHODS FOR THE COLLECTOR-BASE TIME CONSTANT AND FOR THE RESISTIVE PART OF THE COMMON-EMITTER INPUT IMPEDANCE Status: Reaffirmed November 1963, June 1972, April 1981, April 1999, October 2002	JESD284-A	Nov 1963
The test methods described in this Standard are generally applicable to alloy-like devices for which the usual simplified equivalent circuits can be employed. Formerly known as EIA-284-A (November 1963). Became JESD284-A when reaffirmed in October 2002. Committee(s): JC-25 Free download. Registration or login required.
Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1	JEP200	Jun 2024
This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices. Committee(s): JC-70, JC-70.1, JC-70.2 Free download. Registration or login required.
TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES:	JESD23	May 1982
This standard specifies a collection of procedures for testing and character designation of liquid crystal devices. Free download. Registration or login required.
TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS: Status: Reaffirmed May 2023	JESD72A	Mar 2018
This Test Method covers the minimum requirements that should be in effect for the evaluation and acceptance of polymeric materials for use in industrial, military, space, and other special-condition products which may require capabilities beyond standard commercial microelectronics applications. It is not the intent of this Publication to specify a material, but to evaluate the material to assure that the quality and reliability of the microelectronic devices are not compromised. This document replaces JEP105, JEP107 and JEP112. Committee(s): JC-13.5 Free download. Registration or login required.
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications	JESD22-B121	Nov 2023
This test method covers X-ray imaging for terrestrial applications on packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES	JESD22-A120C	Jan 2022
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHOD FOR REAL-TIME SOFT ERROR RATE	JESD89-1B	Jul 2021
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST METHOD FOR QUALIFICATION AND ACCEPTANCE OF PARTICLE GETTERS FOR USE IN HYBRID MICROELECTRONIC APPLICATIONS - SUPERSEDED BY JESD72, June 2001 Status: Rescinded	JEP107	Apr 1985
Committee(s): JC-13.5 Free download. Registration or login required.
TEST METHOD FOR QUALIFICATION AND ACCEPTANCE OF CIRCUIT SUPPORT FILMS FOR USE IN MICROELECTRONIC APPLICATIONS - SUPERSEDED BY JESD72, June 2001 Status: Rescinded	JEP112	Jun 1987
Committee(s): JC-13 Free download. Registration or login required.
TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES	JESD22-B130	Sep 2022
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required.

Standards & Documents Search

TYPE DESIGNATION SYSTEM FOR MICROELECTRONIC DEVICES

TWO-RESISTOR COMPACT THERMAL MODEL GUIDELINE

Two Byte Modules Cards

TSE2002 Serial Presence Detect with Thermal Sensor

TS511X, TS521X Serial Bus Thermal Sensor Device Standard

TS3000 Standalone Thermal Sensor Component

TRANSISTOR, GALLIUM ARSENIDE POWER FET, GENERIC SPECIFICATION:

TRANSIENT VOLTAGE SUPPRESSOR STANDARD FOR THYRISTOR SURGE PROTECTIVE DEVICE:

TRANSIENT DUAL INTERFACE TEST METHOD FOR THE MEASUREMENT OF THE THERMAL RESISTANCE JUNCTION-TO-CASE OF SEMICONDUCTOR DEVICES WITH HEAT FLOW THROUGH A SINGLE PATH

THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES

THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997.

THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)

THERMAL SHOCK

THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD):

THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORS:

THERMAL RESISTANCE FOR TEST METHODS FOR SIGNAL DIODES - SUPERSEDED BY EIA-531, July 1986. See JESD531, April 2002.

THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORS

THERMAL MODELING OVERVIEW

THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)

THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD

THE MEASUREMENT OF TRANSISTOR EQUIVALENT NOISE VOLTAGE AND EQUIVALENT NOISE CURRENT AT FREQUENCIES OF UP TO 20 kHz

THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR SHORT-CIRCUIT FORWARD CURRENT TRANSFER RATIO:

THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS:

TEST TRACE FOR 64 GB - 128 GB SSD

TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES

TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS:

TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C.

Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION:

TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES

TEST METHODS FOR THE COLLECTOR-BASE TIME CONSTANT AND FOR THE RESISTIVE PART OF THE COMMON-EMITTER INPUT IMPEDANCE

Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1

TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES:

TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS:

Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications

TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES

TEST METHOD FOR REAL-TIME SOFT ERROR RATE

TEST METHOD FOR QUALIFICATION AND ACCEPTANCE OF PARTICLE GETTERS FOR USE IN HYBRID MICROELECTRONIC APPLICATIONS - SUPERSEDED BY JESD72, June 2001

TEST METHOD FOR QUALIFICATION AND ACCEPTANCE OF CIRCUIT SUPPORT FILMS FOR USE IN MICROELECTRONIC APPLICATIONS - SUPERSEDED BY JESD72, June 2001

TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES

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