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Committee(s): JC-22.2

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.4

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This publication is intended for power GaAs FET applications requiring high reliability. An accurate measurement of thermal resistance is extremely important to provide the user with knowledge of the FETs operating temperature so that more accurate life estimates can be made. FET failure mechanisms and failure rates have, in general, an exponential dependence on temperature (which is why temperature-accelerated testing is successful). Because of the exponential relationship of failure rate with temperature, the thermal resistance should be referenced to the hottest part of the FET.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.7

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This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-70, JC-70.2

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This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets.

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Committee(s): JC-70.2

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The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.4

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This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14, JC-14.4

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This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis.

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Committee(s): JC-70.1

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These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors.  While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). 

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.7

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This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-70.1

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This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches.

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Committee(s): JC-70, JC-70.1

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The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 provided the forum where various methods were discussed and commonality in approach emerged. The result is that today we have relatively consistent results in measuring and reporting electrical package parameters, as well as specialized tools (e.g., the IPA-510, the interconnect parameter analyzer) which were developed to support the methodology.

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Committee(s): JC-15.2, JC-15

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This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric.

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Committee(s): JC-70, JC-70.2

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This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup.

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Committee(s): JC-70.2

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This publication provides a guideline to suppliers of IC components with a template for documenting the numerical simulation assumptions. In addition this guideline also suggests a model environment to reference when comparing various packages or component suppliers. This publication should improve the communication between the package model suppliers. This publication should improve the communication between the package model supplier and the end user.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-15.2

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This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14, JC-14.1

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This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.4

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This guide has been replaced by JESD241: September 2021.

A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office.

Committee(s): JC-14.2

This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212).

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Committee(s): JC-42.3C

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