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Title	Document #	Date
PRODUCT DISCONTINUANCE Status: Supersededby J-STD-048, November 2014	JESD48C	Dec 2011
This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition on-going requirements to alternate products. Committee(s): JC-14, JC-14.4
PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)	JESD49B.01	Oct 2023
This standard facilitates the procurement and use of semiconductor die products provided in bare or bumped die form, and provides requirements and guidance to die suppliers as to the levels of as-delivered performance, quality and reliability expected. It also reflects the special needs of die product customers in terms of design and application data. Committee(s): JC-13 Free download. Registration or login required.
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS - SUPERSEDED BY EIA-623, July 1994 Status: Superseded	JESD40	Jul 1994
Committee(s): JC-13 Free download. Registration or login required.
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS Status: Rescinded May 2006	EIA623	Jul 1994
Committee(s): JC-13 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A.01	Dec 2022
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35A	Apr 2001
JESD35A was rescinded by the committee in June 2024 and has been superseded by JESD263. The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown. Committee(s): JC-14.2
PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES Status: Reaffirmed September 2021	JESD241	Dec 2015
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document. Committee(s): JC-14.2 Free download. Registration or login required.
PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY	JEP159A	Jul 2015
This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors	JEP199	Apr 2024
This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA):	JEP147	Oct 2003
This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics - to a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component. Committee(s): JC-16, JC-16.2 Free download. Registration or login required.
PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS: Status: Rescinded	JESD92	Aug 2003
JESD92 was rescinded by the committee in June 2024 and has been superseded by JESD263. This document defines a constant voltage stress test procedure for characterizing time-dependent dielectric breakdown or 'wear-out' of thin gate dielectrics used in integrated circuit technologies. The test is designed to obtain voltage and temperature acceleration parameters required to estimate oxide life at use conditions. The test procedure includes sophisticated techniques to detect breakdown in ultra-thin films that typically exhibit large tunneling currents and soft or noisy breakdown characteristics. This document includes an annex that discusses test structure design, methods to determine the oxide electric field in ultra-thin films, statistical models, extrapolation models, and example failure-rate calculations Committee(s): JC-14, JC-14.2
PREPARATION OF OUTLINE DRAWINGS OF SOLID-STATE PRODUCTS FOR JEDEC TYPE REGISTRATION, RESCINDED May 2009 Status: RescindedMay, 2009	EIA308-A	Aug 1981
Note that the terms and definitions contained in EIA308A are still available in the JEDEC dictionary as they are commonly used in the industry. Committee(s): JC-11 Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)	PRN13-NM1	Oct 2013
Item No. 2229.01 (JC-45.3-11-523, JCB-11-102) Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)	PRN13-NM3	Oct 2013
Item No. 2207.14 (JC-45.1-12-284, JCB-12-63) Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS: Status: ReaffirmedSeptember 1981, April 1999	JEP69-B	Nov 1973
This publication indicates preferred pinouts for FETs in various package designs. Committee(s): JC-25 Free download. Registration or login required.
PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING	JESD22-A113I	Apr 2020
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow). Committee(s): JC-14.1 Free download. Registration or login required.
POWER MOSFETS:	JESD24	Jul 1985
This standard contains a listing of terms and definitions and letter symbols; a description of established procedures that are followed in the assignment of semiconductor-industry-type designations to power transistors; electrical verification test; thermal characteristics; and a user's guide. Committee(s): JC-25 Free download. Registration or login required.
POWER MOSFET ELECTRICAL DOSE RATE TEST METHOD: Status: ReaffirmedApril 1999	JEP115	Aug 1989
The purpose of this Test Method is to establish electrical criteria for comparing and specifying power MOSFET performance under high dose rate radiation. Committee(s): JC-25 Free download. Registration or login required.
Power Cycling	JESD22-A122B	Nov 2023
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
POWER AND TEMPERATURE CYCLING	JESD22-A105D	Jan 2020
The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes and simultaneously the operating biases are periodically applied and removed. It is intended to simulate worst case conditions encountered in application environments. The power and temperature cycling test is considered destructive and is only intended for device qualification. This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)	JEP131C	Aug 2018
This publication applies to electronic components and subassemblies product and or process development, manufacturing processes and the associated performance requirements in customer applications. These areas should include, but are not limited to: package design, chip design, process development, assembly, fabrication, manufacturing, materials, quality, service, and suppliers, as well as the process requirements needed for the next assembly. Committee(s): JC-14.4 Free download. Registration or login required.
POD18 - 1.8 V PSEUDO OPEN DRAIN I/O	JESD8-19	Dec 2006
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A.01	Aug 2022
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21C.01	Jun 2022
Editorial, Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required.
POD125 - 1.25 V PSEUDO OPEN DRAIN I/O	JESD8-30A.01	Jun 2022
Editorial Terminology Update. This standard defines the DC and AC single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.25 V Pseudo Open Drain I/Os. The 1.25 V Pseudo Open Drain interface, also known as POD125, is primarily used to communicate with GDDR6 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE	JESD8-24	Aug 2011
This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Committee(s): JC-16 Free download. Registration or login required.
POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE	JESD8-25	Sep 2011
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required.
PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03	JESD301-2	Oct 2022
This standard defines the specification of interface parameters, signaling protocols, and features for PMIC devices used for memory module applications. The designation PMIC5100 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5100 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Item 336.01C Committee(s): JC-40.1 Free download. Registration or login required.
PMIC50x0 Power Management IC Standard	JESD301-1A.02 Rev. 1.8.5	Apr 2023
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5000, PMIC5010 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5000, PMIC5010 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40.1 Free download. Registration or login required.
PMIC5020 Power Management IC Standard Release Number: Version 1.0.1	JESD301-4	Apr 2024
This standard defines the specifications of interface parameters, signaling protocols, and features for PMIC device as used for memory module applications. The designation PMIC5020 refers to the device specified by this document. The purpose is to provide a standard for the PMIC5020 device for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE	MO-339B	May 2024
Item 11-1054 Package Designator: PQFP-N28_I4p0... Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE	MO-356A	Aug 2023
Designator: PQFP-B#[#]_Ip27... Item #: 11-1037 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC MULTI SMALL OUTLINE, 1.20 MM PITCH PACKAGE 1.14 MM PITCH, 15.40 MM BODY WIDTH, RECT FAMILY PACKAGE	MO-354B	Sep 2024
Item: 11-1065 Designator: PMSO-E#_I1p14-... Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)	TO-282A	Jun 2024
Package Designator: PMDF-T5_I2p54... Item # 11-1058 Patents(): Owners: - Otremba, Ralf - Kasztelan, Christian - Fuergut, Edward - Lee, Teck Sim - Wang, Lee Shuang - Kuek, Hsieh Ting - Murugan, Sanjay Kumar Company: - Infineon Technologies AG, 85579 Neubiberg, DE Patent Number (Germany): - DE 102015109073 B4 Title: - Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)	SO-032D	Nov 2024
Designator: SO-032D_PDUtBXC-H736_I1p0-R17p15x78p0Z1p05 Item: 14-231 Cross Reference: N/A Patents(): Patent NO: 9,425,525 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE	MO-340D	Dec 2023
Designator: PDSO_N#[#]_I#-R#x#Z#-CturET0p04 Item: 11-1044 Cross Reference: DR4.8, DR4.16, DR4.20 Patents(): Nexperia BV: 8809121B2 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, RECTANGULAR FAMILY PACKAGE	MO-153I	Aug 2024
Package Designator: PDSO-G#-I##.... Item# - JC11.11-1069 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR PACKAGE	MO-203D	May 2024
Item 11-1051 Package Designator: PDSO-G#_... Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE	MO-359B	Jul 2024
Designator: H-PDSO-G12_12p0-12p0x9p4Z2p8 Item No: 11-1049 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE)	DO-215E	May 2024
Package Designator: P-PDSO-G2... Committee(s): JC-11, JC-11.1, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

PRODUCT DISCONTINUANCE

PROCUREMENT STANDARD FOR KNOWN GOOD DIE (KGD)

PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS - SUPERSEDED BY EIA-623, July 1994

PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS

PROCESS CHARACTERIZATION GUIDELINE

PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS:

PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES

PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors

PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA):

PROCEDURE FOR CHARACTERIZING TIME-DEPENDENT DIELECTRIC BREAKDOWN OF ULTRA-THIN GATE DIELECTRICS:

PREPARATION OF OUTLINE DRAWINGS OF SOLID-STATE PRODUCTS FOR JEDEC TYPE REGISTRATION, RESCINDED May 2009

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-UDIMM RC F0(x8 2R, STACKED)

PRELIMINARY RELEASE FOR JESD21: DDR3 MINI-RDIMM ANNEX D (x8 2R, Planar)

PREFERRED LEAD CONFIGURATION FOR FIELD-EFFECT TRANSISTORS:

PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING

POWER MOSFETS:

POWER MOSFET ELECTRICAL DOSE RATE TEST METHOD:

Power Cycling

POWER AND TEMPERATURE CYCLING

POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)

POD18 - 1.8 V PSEUDO OPEN DRAIN I/O

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

POD135 - 1.35 V PSEUDO OPEN DRAIN I/O

POD125 - 1.25 V PSEUDO OPEN DRAIN I/O

POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE

PMIC5100 POWER MANAGEMENT IC STANDARD, Rev 1.03

PMIC50x0 Power Management IC Standard

PMIC5020 Power Management IC Standard

PLASTIC QUAD FLATPACK, 28 TERMINAL PACKAGE

PLASTIC QUAD FLATPACK 1.27 MM PITCH, 5.00 MM X 6.00 MM RECTANGULAR FAMILY PACKAGE

PLASTIC MULTI SMALL OUTLINE, 1.20 MM PITCH PACKAGE 1.14 MM PITCH, 15.40 MM BODY WIDTH, RECT FAMILY PACKAGE

PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)

PLASTIC DUAL UPPER TO BOTTOM, 1.38 MM X1.00 MM PITCH CONNECTOR (CMT)

PLASTIC DUAL SMALL OUTLINE, SURFACE TERMINAL, WETTABLE FLANK PACKAGE

PLASTIC DUAL SMALL OUTLINE, RECTANGULAR FAMILY PACKAGE

PLASTIC DUAL SMALL OUTLINE, GULL WING, RECTANGULAR PACKAGE

PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE

PLASTIC DUAL SMALL OUTLINE, GULL WING, 2 TERMINAL, RECTANGULAR PACKAGE (DIODE)

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