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This standard is applicable to diodes that are used as voltage regulators and voltage references. It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics.

Committee(s): JC-22, JC-22.2

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Release No. 16. Item 1541.03

Committee(s): JC-42, JC-42.2

JESD21-C Solid State Memory Documents Main Page

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Release No.6

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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Release No.13

Committee(s): JC-42.3, JC-42

JESD21-C Solid State Memory Documents Main Page

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Release No. 10

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance.

Committee(s): JC-14, JC-14.1

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This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device.

Committee(s): JC-42, JC-42.6

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This standard is intended to cover the measurement of noise voltage in voltage regulator diodes in the reverse breakdown region. It describes noise voltage measurements at specified conditions, but may be used as a guide for making such measurements at other than specified conditions. Formerly known as RS-307 and/or EIA-307

Committee(s): JC-22.4

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Release No. 9

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

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The purpose of these user guidelines is to provide background and an example for the use of an infrared (IR) microscope to determine die temperature of electronic devices for calculations such as thermal resistance.

Committee(s): JC-25

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This document replaces all past versions, however JESD220E, January 2020 (V 3.1), is available for reference only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface.

Committee(s): JC-64.1

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This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Item 206.25

Committee(s): JC-64.1

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This document has been superseded by JESD223D, January 2018, however is available for reference only.

Committee(s): JC-64.1

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This document has been superseded by JESD220F, August 2022, however is available for reference only.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64.1

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This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only.

This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model is referencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10 (SCSI) SPC and SBC standards. Item 133.00B

Committee(s): JC-64.1

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The primary objective of this test standard is to specify the test cases for UFS device protocol conformance testing. This test standard provides test cases for checking the functions defined in the following target standard: JESD220. Universal Flash Storage (UFS) Standard version 1.1A. MIPI M-PHY and MIPI UniPro test cases are not in the scope of this document. Item 400.36

Committee(s): JC-64.5

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This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34

Patents(): WD: 9,323,657

Committee(s): JC-64.1

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This standard specifies the extension specification of the UFS electrical interface and the memory device.

PLEASE NOTE: Revision and renumbering of JESD231 Version 1.0, August 2022

Committee(s): JC-64, JC-64.1

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This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range.  The standard bridges a number of existing JEDEC standards in the JESD8-x family to facilitate applications that operate over an ultra-wide power supply voltage range in order to achieve lower power dissipation or higher performance. 

Committee(s): JC-16

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