Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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STANDARD METHOD FOR MEASURING AND USING THE TEMPERATURE COEFFICIENT OF RESISTANCE TO DETERMINE THE TEMPERATURE OF A METALLIZATION LINE:Status: Reaffirmed October 2012, September 2018 |
JESD33B | Feb 2004 |
This newly revised test method provides a procedure for measuring the temperature coefficient of resistance, TCR(T), of thin-film metallizations used in microelectronic circuits and devices. Procedures are also provided to use the TCR(T) to determine the temperature of a metallization line under Joule-heating conditions and to determine the ambient temperature where the metallization line is used as a temperature sensor. Originally, the method was intended only for aluminum-based metallizations and for other metallizations that satisfy the linear dependence and stability stipulations of the method. The method has been revised to make it explicitly applicable to copper-based metallizations, as well, and at temperatures beyond where the resistivity of copper is no longer linearly dependent on temperature (beyond approximately 200 °C). Using the TCR(T) measured for copper in the linear-dependent region, a factor is used to correct the calculated temperature at these higher temperatures. Committee(s): JC-14.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Change Record Methodology |
SPP-021A | Jan 2006 |
Item 11.2-710S Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Definition of DAMBAR Protrusion and Intrusion. |
SPP-006 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Document Procedure. |
SPP-001 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Grid Array Terminal Position Numbering |
SPP-010B | May 2014 |
Free download. Registration or login required. |
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Standard Practices and Procedures - Gullwing Lead Dimensioning. |
SPP-008 | Sep 1991 |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Inactivation and Rescission. |
SPP-016 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Inclusion of Nominal Dimensions. |
SPP-009 | Sep 1991 |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - J Lead; Dimensioning of Lead Contact Points. |
SPP-011 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Lead Finish and base Metal Specification. |
SPP-004 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Measuring Stand-off Heights of Packages |
SPP-019-A | Jul 2001 |
Clarification on how to measure A1.
Item 11.2-595S
Committee(s): JC-11.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Metrication. |
SPP-003C | Mar 2006 |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Module Insertion Procedure for DIMM and miniDIMM Connectors |
SPP-023B | Feb 2013 |
Item 11.11-781(S) Free download. Registration or login required. |
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Standard Practices and Procedures - Mold Flash, Interlead Flash, Gate Burrs and Protrusion for Plastic Packages. Item 11.2-379. |
SPP-014 | Jul 1994 |
Free download. Registration or login required. |
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Standard Practices and Procedures - Package Variation Designators |
SPP-025C | Aug 2018 |
Item No. 11.2-951(S) Committee(s): JC-11.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Pin #1 Mark and Lead-Numbering Convention for Dual-In-Line Packages with Standard and Reverse-Bend Lead Form. |
SPP-012 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Pin #1 Mark Function and Location. |
SPP-002 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Pin #1 orientation for TAB Packages. |
SPP-005 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Procedure for Making Editorial Corrections to Published Documents. |
SPP-018 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783 |
SPP-024A | Mar 2009 |
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Free download. Registration or login required. |
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Standard Practices and Procedures - Registered and Standard Outlines |
SPP-013A | Oct 2014 |
Item 11.2-886(E). This document has been editorially updated to provide template examples. Committee(s): JC-11.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Requirements for Applying Material and Finish Specifications to Selected Mechanical Outlines. |
SPP-015 | |
Committee(s): JC-11 Free download. Registration or login required. |
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Standard Practices and Procedures - Standard Overall Profile Height Codes for Packages. RESCINDED, March 2009Status: RescindedMarch 2009 |
SPP-017-C | Nov 2004 |
Committee(s): JC-11.2 Free download. Registration or login required. |
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Standard Practices and Procedures - Thermal Pad Requirements. Item 11.2-748(S) |
SPP-022B | Mar 2006 |
Free download. Registration or login required. |
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Standard Practices and Procedures - Use of -PROPOSED- on Ballots. |
SPP-007 | |
Committee(s): JC-11 Free download. Registration or login required. |
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STANDARD SPECIFICATION FOR DESCRIPTION OF B SERIES CMOS DEVICES: |
JESD13-B | May 1980 |
This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required. |
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Standard Template for JEDEC Module Standards |
MODULE4.20.1 | Oct 2001 |
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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STANDARD TEST AND PROGRAMMING LANGUAGE (STAPL): |
JESD71 | Aug 1999 |
STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices (PLDs) offered by a variety of PLD vendors. STAPL is also suitable for testing 1149.1-compliant devices. Committee(s): JC-42.1 Free download. Registration or login required. |
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STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES |
JESD203 | Nov 2005 |
This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to th Free download. Registration or login required. |
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STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) - LEAD (Pb) CONTENTReaffirmed June 2023 |
JESD213A | Apr 2017 |
This document is intended to be used by Original Component Manufacturers who deliver electronic components and Original Equipment Manufacturers who are the platform system integrators. It is intended to be applied prior to delivery by the OCMs and may be used by OEM system engineers and procuring activities as well as U.S Government Department of Defense system engineers, procuring activities and repair centers. This Standard establishes the instrumentation, techniques, criteria, and methods to be utilized to quantify the amount of Lead (Pb) in Tin-Lead (Sn/Pb) alloys and electroplated finishes containing at least 3 weight percent (wt%) Lead (Pb) using X-Ray Fluorescence (XRF) equipment. Reaffirmed June 2023
Committee(s): JC-13 Free download. Registration or login required. |
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STANDARD TEST PROCEDURE FOR NOISE MARGIN MEASUREMENTS FOR SEMICONDUCTOR LOGIC GATING MICROCIRCUITSStatus: Rescinded, October 2008 |
JESD390A | Feb 1981 |
Reaffirmed September 2003 Free download. Registration or login required. |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed 04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. Committee(s): JC-14 Free download. Registration or login required. |
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STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST |
JESD22-A101D.01 | Jan 2021 |
This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Free download. Registration or login required. |
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Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices |
JEP150A | Dec 2023 |
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Free download. Registration or login required. |
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STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS |
JESD47L | Dec 2022 |
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Available for purchase: $87.38 Add to Cart Paying JEDEC Members may login for free access. |
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STUB SERIES TERMINATED LOGIC FOR 1.8 V (SSTL_18): |
JESD8-15A | Sep 2003 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. Committee(s): JC-16 Free download. Registration or login required. |
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Style Manual for Standards and Other Publications of JEDEC |
JM7A | Jul 2024 |
This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association. Committee(s): JC-10 Free download. Registration or login required. |
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SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERSStatus: Reaffirmed November 1999, May 2003 |
JEP103A | Jul 1996 |
In order to improve understanding between manufacturers and users, a consistent set of product-documentation classifications associated with the stages of product development. Committee(s): JC-10 Free download. Registration or login required. |
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SUPERSEDED BY THE TEST METHODS INDICATED BY 'JESD22-'Status: Superseded |
JESD22- B | Jan 2000 |
A complete set of test methods can be obtained from Global Engineering Documents Committee(s): JC-14.1 |