Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
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Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package |
MO-346A.01 | Jun 2023 |
Designator: PQFP-B#[#]_I0p65... Item: 11-981E, Access STP Files for MO-346A Cross Reference: N/A Committee(s): JC-11.11 Free download. Registration or login required. |
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ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2022 | Jun 2023 |
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Free download. Registration or login required. |
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GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTSStatus: Reaffirmed May 2023 |
JEP142 | May 2023 |
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Free download. Registration or login required. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. Committee(s): JC-14 Free download. Registration or login required. |
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Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification |
JEP114A | May 2023 |
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Free download. Registration or login required. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download. Registration or login required. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required. |
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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARDRelease Number: Version 1.5.1 |
JESD300-5B.01 | May 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee(s): JC-40.1 Free download. Registration or login required. |
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REGISTRATION - 288 PIN DDR5 DIMM SMT, 0.85 MM PITCH SOCKET OUTLINE |
SO-023D | May 2023 |
Designator: PDXC-LO288-I0p85-R162p0x6p5Z21p3-N5p20S3p1Z0p2 Item: 11.14-216, Access STP Files for SO-023C Cross Reference: MO-329, GS-010C
Patents(): CN 202759077 U Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR4 NVDIMM-N Design Standard |
JESD248A.01 | Apr 2023 |
Terminology update. This standard defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Double Data Rate, Synchronous SDRAM Non-Volatile Dual In-Line Memory Modules with NAND Flash backup (DDR4 NVDIMM-N). A DDR4 NVDIMM-N is a Hybrid Memory Module with a DDR4 DIMM interface consisting of DRAM that is made non-volatile through the use of NAND Flash. Committee(s): JC-45.6 Available for purchase: $123.36 Add to Cart Paying JEDEC Members may login for free access. |
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STANDARD TEST STRUCTURE FOR RELIABILITY ASSESSMENT OF AlCu METALLIZATIONS WITH BARRIER MATERIALSStatus: Reaffirmed 04/17/2023 |
JESD87 | Apr 2023 |
This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. Committee(s): JC-14.2, JC-14.21 Free download. Registration or login required. |
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STANDARD METHOD FOR CALCULATING THE ELECTROMIGRATION MODEL PARAMETERS FOR CURRENT DENSITY AND TEMPERATURE:Status: Reaffirmed 4/17/23 |
JESD63 | Apr 2023 |
This method provides procedures to calculate sample estimates and their confidence intervals for the electromigration model parameters of current density and temperature. The model parameter for current density is the exponent (n) to which the current density is raised in Black's equation. The parameter for temperature is the activation energy for the electromigration failure process. Committee(s): JC-14.2 Free download. Registration or login required. |
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Registration - Shipping and Handling Tray for M.2 Type 2280 SSD Microelectronic Assembly |
CO-038A | Apr 2023 |
Designator: N/A Committee(s): JC-11.5 Free download. Registration or login required. |
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Registration - Shipping and Handling Tray for M.2 Type 2230 Microelectronic Assembly |
CO-039A | Apr 2023 |
Designator: N/A Committee(s): JC-11.5 Free download. Registration or login required. |
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Temperature Cycling |
JESD22-A104F.01 | Apr 2023 |
This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch |
MO-355A | Apr 2023 |
Designator: PQFP-E#_I0p65-R... Committee(s): JC-11.11 Free download. Registration or login required. |
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Graphics Double Data (GDDR4) SGRAM StandardRelease Number: 16 |
SDRAM3.11.5.8 R16.01 | Mar 2023 |
Item 1600.41, Terminology Update This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices. Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications |
JESD82-27.01 | Mar 2023 |
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required. |
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Fully Buffered DIMM Design for Test, Design for Validation (DFx) |
JESD82-28A.01 | Mar 2023 |
Terminology update. This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Free download. Registration or login required. |
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RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE |
JESD207.01 | Mar 2023 |
Terminology update. This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component. Committee(s): JC-61 Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD |
JESD232A.01 | Mar 2023 |
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required. |
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SILICON RECTIFIER DIODES: |
JESD282B.02 | Mar 2023 |
Terminology update. This legacy document is a comprehensive users’ guide for silicon rectifier diode applications. Committee(s): JC-22.2 Free download. Registration or login required. |
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DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS |
JESD82-13A.01 | Mar 2023 |
Terminology update. Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications Committee(s): JC-40 Free download. Registration or login required. |
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JEDEC Legal Guidelines |
JM5.01 | Mar 2023 |
Terminology update. This document sets forth the best judgment of the standards of conduct and legal restraints that must be observed to protect against violations of the law. Free download. Registration or login required. |
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COMPACT THERMAL MODEL OVERVIEW |
JESD15-1.01 | Mar 2023 |
Terminology update. This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. Free download. Registration or login required. |
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RADIO FRONT END - BASEBAND (RF-BB) INTERFACE |
JESD96A.01 | Mar 2023 |
Terminology update. This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC). Committee(s): JC-61 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package |
MO-210R | Mar 2023 |
Designator: PBGA-B#[#]_I0p...
Item: 11.11-988, Access STP Files for MO-210R Cross Reference: DG4.5 https://www.jedec.org/filebrowser/download/1625 Patents(): May apply: Micron: 6,048,753. Tessera: 5,950,304; and 6,133,627 Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package |
MO-352A.01 | Mar 2023 |
Designator: PBGA-B#[#}_I0p4... Committee(s): JC-11.11 Free download. Registration or login required. |
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DDR5 Registering Clock Driver Definition (DDR5RCD03)Release Number: 1.00 |
JESD82-513 | Feb 2023 |
This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053. Free download. Registration or login required. |
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Annex F, R/C F, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design SpecificationRelease Number: 33 |
MODULE4.20.26.F | Feb 2023 |
This specification defines the electrical and mechanical requirements for Raw Card F, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.43. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel) |
JEP130C | Feb 2023 |
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Free download. Registration or login required. |
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DDR5 Registering Clock Driver Definition (DDR5RCD02)Release Number: Rev. 1.00 |
JESD82-512 | Feb 2023 |
This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052. Free download. Registration or login required. |
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Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion |
JEP195 | Feb 2023 |
This document elaborates on the information given in JEP184 regarding the long-time stability of device parameters under static conditions and under application near switching conditions. Free download. Registration or login required. |
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Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs |
JEP194 | Feb 2023 |
This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric. Free download. Registration or login required. |
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DEFINITION OF THE SSTU32S869 AND SSTU32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS |
JESD82-12A.01 | Feb 2023 |
Terminology update. Committee(s): JC-40 Free download. Registration or login required. |
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DEFINITION OF THE SSTUA32S868 AND SSTUA32D868 REGISTERED BUFFER WITH PARITY FOR 2R X 4 DDR2 RDIMM APPLICATIONS |
JESD82-17.01 | Feb 2023 |
(Terminology update.) This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications. Free download. Registration or login required. |
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FBDIMM: ARCHITECTURE AND PROTOCOL |
JESD206.01 | Feb 2023 |
Terminology update. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required. |
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INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES |
JESD82-22.01 | Feb 2023 |
Terminology update. Free download. Registration or login required. |
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DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS: |
JESD82-7A.01 | Feb 2023 |
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. Free download. Registration or login required. |