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Title	Document #	Date
ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD: Status: ReaffirmedMarch 2001, October 2002	JESD24-11	Aug 1996
Test method to measure the equivalent resistance of the gate to source of a power MOSFET. Committee(s): JC-25 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996. Status: Superseded	JESD29-A	Jul 1996
Committee(s): JC-14.3 Free download. Registration or login required.
MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES: Status: Reaffirmed	EIA318-B	Jul 1996
This standard describes the measurement of signal diodes (IF <=500mA dc) reverse recovery times of less than 300 ns duration. It may, however, also be used for the measurement of longer recovery times. This standard is also intended to establish a method which to characterize the test fixture used for this measurement. Committee(s): JC-22.4 Free download. Registration or login required.
SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERS Status: Reaffirmed November 1999, May 2003	JEP103A	Jul 1996
In order to improve understanding between manufacturers and users, a consistent set of product-documentation classifications associated with the stages of product development. Committee(s): JC-10 Free download. Registration or login required.
Registration - Thin Matrix Tray for Handling and Shipping Small Outline J- Lead Packages (SOJ). Item 11.5-446.	CO-032-A	Jun 1996
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:	JESD36	Jun 1996
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR CHAIN DESCRIPTION FILE:	JESD32	Jun 1996
This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the configuration of a programming chain made up of devices that can be connected in some serial fashion. No assumptions are made about how data is used by the device, nor about the nature or configuration of the control signals that affect programming. It will support devices configured using electrically-erasable(EE), Flash, SRAM, or any other reconfigurable cell. For devices programmed via an IEEE programmable devices in the same chain. Committee(s): JC-42.1 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:	JESD55	May 1996
The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required.
GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS:	JEP126	May 1996
This publication provides a guideline to suppliers of IC components with a template for documenting the numerical simulation assumptions. In addition this guideline also suggests a model environment to reference when comparing various packages or component suppliers. This publication should improve the communication between the package model suppliers. This publication should improve the communication between the package model supplier and the end user. Committee(s): JC-15.2 Free download. Registration or login required.
Standard - Thin Matrix Tray for MQFP Shipping. Item 11.5-436S	CS-004-B	Apr 1996
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - TSOP-I, Thin Matrix Tray for Shipping and Handling. Item 11.4-437S.	CS-008-A	Mar 1996
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:	JESD54	Feb 1996
The purpose is to provide a standard of BiCMOS Logic series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Committee(s): JC-40 Free download. Registration or login required.
ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35-2	Feb 1996
JESD35-2 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures. Committee(s): JC-14.2
MANAGEMENT OF COMPONENT OBSOLESCENCE BY GOVERNMENT CONTRACTORS: RESCINDED, October 2002 Status: RescindedOctober 2002	JESD53	Jan 1996
Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Nibble Wide SRAM	SRAM3.7.3	Dec 1995
Release No.5 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide TTL SRAM	SRAM3.7.1	Dec 1995
Release No. 5 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE)	JESD51	Dec 1995
This standard and its subsequent addendum's, provides a standard for thermal measurement that, if followed fully, will provide correct and meaningful data that will allow for determination of junction temperature for specific conditions. The data can be used for package design evaluation, device characterization and reliability predictions. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE):	JESD51- 1	Dec 1995
The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. This method will provide a basis for comparison of different devices housed in the same electronic package or similar devices housed in different electronic packages. Committee(s): JC-15.1 Free download. Registration or login required.
GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999. Status: RescindedNovember 1999	JEP124	Dec 1995
Committee(s): JC-14.4 Free download. Registration or login required.
STANDARD FOR FAILURE ANALYSIS REPORT FORMAT: Status: Rescinded January 2025	JESD38	Dec 1995
This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets. Committee(s): JC-14.4 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:	JESD52	Nov 1995
This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike. Committee(s): JC-40 Free download. Registration or login required.
JEDEC REQUIREMENTS FOR CLASS B MICROCIRCUITS Status: Rescinded, May 2006	JEP101-C	Nov 1995
Committee(s): JC-13.2 Free download. Registration or login required.
MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999. Status: Rescinded, May 2000	JESD22-A112-A	Nov 1995
J-STD-020 is now on revision F. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS:	JEP123	Oct 1995
The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 provided the forum where various methods were discussed and commonality in approach emerged. The result is that today we have relatively consistent results in measuring and reporting electrical package parameters, as well as specialized tools (e.g., the IPA-510, the interconnect parameter analyzer) which were developed to support the methodology. Committee(s): JC-15.2, JC-15 Free download. Registration or login required.
Registration - Thick Matrix Mini Tray For Shipping and Handling. Item 11.5-426.	CO-031-A	Oct 1995
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Thin Matrix Mini Tray for Shipping and Handling. Item 11.5-427.	CO-030-A	Oct 1995
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS Status: Rescinded	JESD35-1	Sep 1995
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. Committee(s): JC-14.2
ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS:	JESD8-6	Aug 1995
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz. Committee(s): JC-16 Free download. Registration or login required.
REVERSE RECOVERY CHARACTERISTICS OF SILICON DIODES: RESCINDED June 2002. Status: Rescinded	JESD41	May 1995
Committee(s): JC-22.1 Free download. Registration or login required.
GENERAL REQUIREMENTS FOR DISTRIBUTORS OF MILITARY SEMICONDUCTOR DEVICES: Status: Rescinded	JEP109-C	Mar 1995
Superseded by JESD31-A, June 2001. Committee(s): JC-13 Free download. Registration or login required.
Nibble Wide ECL SRAM	SRAM3.7.4	Dec 1994
Release No.04 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
MEASUREMENT METHOD FOR THERMAL RESISTANCE OF BRIDGE RECTIFIER ASSEMBLIES: RESCINDED, June 2002. Replaced by JESD282-B. Status: RescindedJune 2002	JESD45	Dec 1994
Committee(s): JC-22.2 Free download. Registration or login required.
Registration - Tray for Handling and Shipping of PGA Packages. Item 11.5-382	CO-010-E	Nov 1994
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES: Status: ReaffirmedOctober 2002	JESD24-10	Aug 1994
Test method to measure the reverse recovery characteristics of the drain source diode of a power MOSFET. Committee(s): JC-25 Free download. Registration or login required.
Registration - Small Outline J-Lead (SOJ) Ceramic Chip Carrier, .415 inch Body, .050 inch Lead Spacing. R-CDSO-J.	MO-147-A	Jul 1994
Item 11.10-321 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS - SUPERSEDED BY EIA-623, July 1994 Status: Superseded	JESD40	Jul 1994
Committee(s): JC-13 Free download. Registration or login required.
PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS Status: Rescinded May 2006	EIA623	Jul 1994
Committee(s): JC-13 Free download. Registration or login required.
Standard Practices and Procedures - Mold Flash, Interlead Flash, Gate Burrs and Protrusion for Plastic Packages. Item 11.2-379.	SPP-014	Jul 1994
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS Status: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999.	JESD8-1A	Jun 1994
Committee(s): JC-16 Free download. Registration or login required.
ADDENDUM No. 1 to JESD8: INTERFACE STANDARD FOR LOW VOLTAGE TTL-COMPATIBLE (LVTTL) VLSI DIGITAL CIRCUITS Status: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999.	JESD8-1	Jun 1994
Committee(s): JC-16 Free download. Registration or login required.

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Standards & Documents Search

ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD:

FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996.

MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES:

SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERS

Registration - Thin Matrix Tray for Handling and Shipping Small Outline J- Lead Packages (SOJ). Item 11.5-446.

STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:

STANDARD FOR CHAIN DESCRIPTION FILE:

STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

GUIDELINE FOR DEVELOPING AND DOCUMENTING PACKAGE ELECTRICAL MODELS DERIVED FROM COMPUTATIONAL ANALYSIS:

Standard - Thin Matrix Tray for MQFP Shipping. Item 11.5-436S

Standard - TSOP-I, Thin Matrix Tray for Shipping and Handling. Item 11.4-437S.

STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

ADDENDUM No. 2 to JESD35 - TEST CRITERIA FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS:

MANAGEMENT OF COMPONENT OBSOLESCENCE BY GOVERNMENT CONTRACTORS: RESCINDED, October 2002

Nibble Wide SRAM

Bit Wide TTL SRAM

METHODOLOGY FOR THE THERMAL MEASUREMENT OF COMPONENT PACKAGES (SINGLE SEMICONDUCTOR DEVICE)

INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE):

GUIDELINES FOR THE PACKING, HANDLING, AND REPACKING OF MOISTURE-SENSITIVE COMPONENTS - SUPERSEDED BY J-STD-033, May 1999.

STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:

STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:

JEDEC REQUIREMENTS FOR CLASS B MICROCIRCUITS

MOISTURE-INDUCED STRESS SENSITIVITY FOR PLASTIC SURFACE MOUNT DEVICES - SUPERSEDED BY J-STD-020A, April 1999.

GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS:

Registration - Thick Matrix Mini Tray For Shipping and Handling. Item 11.5-426.

Registration - Thin Matrix Mini Tray for Shipping and Handling. Item 11.5-427.

ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICS

ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS:

REVERSE RECOVERY CHARACTERISTICS OF SILICON DIODES: RESCINDED June 2002.

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF MILITARY SEMICONDUCTOR DEVICES:

Nibble Wide ECL SRAM

MEASUREMENT METHOD FOR THERMAL RESISTANCE OF BRIDGE RECTIFIER ASSEMBLIES: RESCINDED, June 2002. Replaced by JESD282-B.

Registration - Tray for Handling and Shipping of PGA Packages. Item 11.5-382

ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES:

Registration - Small Outline J-Lead (SOJ) Ceramic Chip Carrier, .415 inch Body, .050 inch Lead Spacing. R-CDSO-J.

PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS - SUPERSEDED BY EIA-623, July 1994

PROCUREMENT QUALITY OF SOLID STATE COMPONENTS BY GOVERNMENT CONTRACTORS

Standard Practices and Procedures - Mold Flash, Interlead Flash, Gate Burrs and Protrusion for Plastic Packages. Item 11.2-379.

INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS

ADDENDUM No. 1 to JESD8: INTERFACE STANDARD FOR LOW VOLTAGE TTL-COMPATIBLE (LVTTL) VLSI DIGITAL CIRCUITS

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