Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
Date![]() |
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80 Pin EEPROM SIMM |
MODULE4.4.7 | Dec 1997 |
Release No.8 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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72 Pin DRAM SIMM |
MODULE4.4.2 | Dec 1997 |
Release No.8 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - Stacked TSOPII Package (2 and 4 High). Item 11.11-429.April 2003 |
MO-201-A | Oct 1997 |
This outline has been inactivated, please see attachment. The file can be located by going to the JEP95 Main Page, under Microelectronic Outlines, Archives. Committee(s): JC-11 Free download. Registration or login required. |
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Dynamic Random Access Memory (DRAM) Table of Contents |
DRAM3.9.TOC | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide ECL SRAM |
SRAM3.7.6 | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide ECL SRAM |
SRAM3.7.2 | Jul 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EEPROM Introduction |
EEPROM3.5 | Jul 1997 |
Release No.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide |
EPROM3.4.1 | Jul 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EPROM Introduction |
EPROM3.4 | Jul 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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278 Pin Buffered SDRAM DIMM |
MODULE4.6.1 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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4.6 Table of Contents - Sixteen Byte Modules |
MODULE4.6 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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112 Pin MPDRAM DIMM |
MODULE4.4.6 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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88 Pin DRAM SO-DIMM |
MODULE4.4.5 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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72 Pin DRAM SO-DIMM |
MODULE4.4.4 | Jun 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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88 Pin DRAM CardStatus: Reaffirmed |
MODULE4.4.3 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Four Byte Modules and Cards Table of Contents |
MODULE4.4.TOC | Jun 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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64 & 72 Pin ZIP/SIMM SRAM Module |
MODULE4.4.1 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Two Byte Modules Cards |
MODULE4.3 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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One Byte Modules |
MODULE4.2 | Jun 1997 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Memory Module Nomenclature |
SPD4.1.1 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Bit Wide SDRAM |
SDRAM3.11.1 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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MPDRAM Optional Features |
MPDRAM3.10.4 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Byte Wide MPDRAM |
MPDRAM3.10.2 | Jun 1997 |
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Nibble Wide MPDRAM |
MPDRAM3.10.1 | Jun 1997 |
Release No.9 Committee(s): JC-42.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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BOND WIRE MODELING STANDARD: |
JESD59 | Jun 1997 |
This standard describes the modeling of a bond wire from an integrated circuit (IC) die to a package lead in a ball or wedge type wire bond configuration. Committee(s): JC-15.2 Free download. Registration or login required. |
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QUALITY SYSTEM ASSESSMENT - SUPERSEDED BY ANSI/EIA-670, June 1997.Status: Superseded |
JESD39-A | Jun 1997 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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Rescinded - Plastic Ball Grid Array (PBGA) Family 1.0, 1.27, and 1.50 mm Pitch. S-PXGA-X/PBGA.Status: Elevated to MS-034 |
MO-151-D | Jun 1997 |
Item 11.11-555. Committee(s): JC-11 |
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THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997.Status: ElevatedSeptember 1997 |
JEP129 | Feb 1997 |
Committee(s): JC-15.1 Free download. Registration or login required. |
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COMPONENT PROBLEM ANALYSIS AND CORRECTIVE ACTION REQUIREMENTS - SUPERSEDED BY EIA-671, November 1996.Status: Superseded |
JESD43 | Nov 1996 |
Committee(s): JC-14.4 Free download. Registration or login required. |
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GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING:Status: Rescinded September 2021 (JC-14.2-21-182) |
JEP128 | Nov 1996 |
This guide has been replaced by JESD241: September 2021. Committee(s): JC-14.2 |
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ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS |
JESD8-8 | Aug 1996 |
This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz. Committee(s): JC-16 Free download. Registration or login required. |
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Design Requirements - Metric Small Outline J-Leaded Package Design Guide |
DG-4.13 | Aug 1996 |
Free download. Registration or login required. |
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LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES: |
JESD51- 3 | Aug 1996 |
This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, trace thickness, and routing considerations. Application includes still air and moving air thermal tests. Committee(s): JC-15.1 Free download. Registration or login required. |
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ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD:Status: ReaffirmedMarch 2001, October 2002 |
JESD24-11 | Aug 1996 |
Test method to measure the equivalent resistance of the gate to source of a power MOSFET. Committee(s): JC-25 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORING - SUPERSEDED BY EIA/ANSI-659, July 1996.Status: Superseded |
JESD29-A | Jul 1996 |
Committee(s): JC-14.3 Free download. Registration or login required. |
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MEASUREMENT OF REVERSE RECOVERY TIME FOR SEMICONDUCTOR SIGNAL DIODES:Status: Reaffirmed |
EIA318-B | Jul 1996 |
This standard describes the measurement of signal diodes (IF <=500mA dc) reverse recovery times of less than 300 ns duration. It may, however, also be used for the measurement of longer recovery times. This standard is also intended to establish a method which to characterize the test fixture used for this measurement. Committee(s): JC-22.4 Free download. Registration or login required. |
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SUGGESTED PRODUCT-DOCUMENTATION, CLASSIFICATIONS, AND DISCLAIMERSStatus: Reaffirmed November 1999, May 2003 |
JEP103A | Jul 1996 |
In order to improve understanding between manufacturers and users, a consistent set of product-documentation classifications associated with the stages of product development. Committee(s): JC-10 Free download. Registration or login required. |
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Registration - Thin Matrix Tray for Handling and Shipping Small Outline J- Lead Packages (SOJ). Item 11.5-446. |
CO-032-A | Jun 1996 |
Free download. Registration or login required. |
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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES: |
JESD36 | Jun 1996 |
This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses. Committee(s): JC-40 Free download. Registration or login required. |
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STANDARD FOR CHAIN DESCRIPTION FILE: |
JESD32 | Jun 1996 |
This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the configuration of a programming chain made up of devices that can be connected in some serial fashion. No assumptions are made about how data is used by the device, nor about the nature or configuration of the control signals that affect programming. It will support devices configured using electrically-erasable(EE), Flash, SRAM, or any other reconfigurable cell. For devices programmed via an IEEE programmable devices in the same chain. Committee(s): JC-42.1 Free download. Registration or login required. |