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Title	Document #	Date
SPD Annex B, Table of Superset Memory Types	SPD4.1.2.2	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SRAM Introduction	SRAM3.7	Oct 2001
Release No. 11 Committee(s): JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS	JESD28-1	Sep 2001
This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis techniques. Committee(s): JC-14.2 Free download. Registration or login required.
Registration - Thermally Enhanced Low Profile Plastic Dual, Flat No Lead Package. L-PDFP-N. Item 11.10-412	MO-232-A	Aug 2001
Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:	JESD73-2	Aug 2001
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:	JESD73-1	Aug 2001
This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices. Committee(s): JC-40 Free download. Registration or login required.
STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:	JESD76-3	Aug 2001
This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.1 Free download. Registration or login required.
REGISTRATION - Thermally enhanced single in-line surface mount package. 21.50 mm Body Width, 1.40 mm Lead Pitch. R-PSIP-Fxx. Item 11.11-590.	MO-231-A	Aug 2001
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:	JESD75-3	Jul 2001
This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:	JESD75-2	Jul 2001
This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
Standard Practices and Procedures - Measuring Stand-off Heights of Packages	SPP-019-A	Jul 2001
Clarification on how to measure A1. Item 11.2-595S Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Quad Flatpack (PQFP) Outline with Exposed Heat Sink. Thermally Enhanced PQFPs. Addition of standard height, variations BA, BB, BC, BD, and BE with Exposed Heat Sink.	MO-204-B	Jun 2001
Item 11.11-586 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT:	JESD51-11	Jun 2001
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Pin Grid Array (PGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-11 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):	JESD76-1	Jun 2001
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION):	JESD76-2	Jun 2001
This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
Registration - Extremely Thin, Two Row Cavity Down, 0.50 mm Pitch BGA Family. The addition of -2, max matrix, variations to XFBGA. Item 11.11-604.	MO-221-C	Jun 2001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
JEP95 Registrations Main Page	JEP95 Index	Apr 2001
This page will provide a link to the Master Index for JEP95. It also provides a link to 'index by device type' as well as the table of contents for each section within JEP95. For older outlines that have been archived, they can be accessed through this page. Committee(s): JC-11 JEP95 Registrations Main Page See JEP95 Index information
PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS: Status: Rescinded	JESD35A	Apr 2001
JESD35A was rescinded by the committee in June 2024 and has been superseded by JESD263. The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown. Committee(s): JC-14.2
Registration - Plastic Small Outline Package with Exposed Heat Sink.	MO-230-A	Mar 2001
Item 11.11-574 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Square, Dual Pitch, FBGA Family. Item 11.11-581.	MO-228-A	Mar 2001
Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Bottom Terminal Ceramic Chip Carrier Family. Item 11.10-408.	TO-276-A	Feb 2001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Change the A4 dimension and value in the Plastic Small Outline Heatslug Package , 7.50 mm Body Wide, 1.0 mm Lead Pitch (H-PDSO-G). Item 11.11-589.	MO-226-B	Feb 2001
Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic SOP, 13.30 mm Wide Body, 1.27 mm Pitch, with addition of a 90 lead Small Outline Package as variation CA. Item 11.11-571.	MO-180-B	Feb 2001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - Low/Thin Profile Plastic Quad Flat Package, 2.00 mm Footprint, Optional Heat. Item 11.11-521S.	MS-026-D	Jan 2001
Clarification to note 15 of the Low Profile PQFP registration MS-026 as issue D. Item 11.11-577s Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 144 Pin Small Outline Dual-In-Line Memory Module (DIMM) Family 0.8 mm Lead Centers with addition of optional beveled edge to SODIMM Family. Item 11.14-048.	MO-190-D	Jan 2001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING: Status: ReaffirmedOctober 2012	JEP139	Dec 2000
This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking. Committee(s): JC-14.2 Free download. Registration or login required.
Registration - Addition of variations, BA, BB, BC, and BD, to Plastic, Surface Mounted Header Family. Item 11.10-406	MO-169-B	Nov 2000
Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Flange Mounted, 2 Lead, Power Package. Item 11.10-405	TO-275-A	Nov 2000
Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 232 Pin DDR SDRAM DIMM Family, 1.00 mm Pitch. Item 11.14-042 03/2003	MO-227-A	Nov 2000
This outline has been inactivated, please see attachment. The file can be located by going to the JEP95 Main Page, under Microelectronic Outlines, Archives. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 210 Pin SDRAM Dual-In-Line Memory Module (DIMM) Family, 1.00 mm Contact Centers. Item 11.14-039. This Outline is Now Inactive. Item 11.14-047.	MO-215-A	Nov 2000
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
144 Pin SGRAM/SDRAM SO-DIMM Family	MODULE4.5.8	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM	MODULE4.5.13	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin DIMM Family Supplementary Design Standards	MODULE4.5.12	Oct 2000
Release No.10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:	JESD64-A	Oct 2000
The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:	JESD82	Jul 2000
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333. Committee(s): JC-40 Free download. Registration or login required.
TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS:	JESD51-10	Jul 2000
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Dual-Inline Packages (DIP) and Single-Inline Packages (SIP). It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-10 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
Word Wide DRAM	DRAM3.9.4	Jul 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS:	JESD51- 9	Jul 2000
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of ball grid array (BGA) and land grid array (LGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-9 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
Design Requirements - Quad Flatpack	DG-4.4A	Jun 2000
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules

Standards & Documents Search

SPD Annex B, Table of Superset Memory Types

SRAM Introduction

Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS

Registration - Thermally Enhanced Low Profile Plastic Dual, Flat No Lead Package. L-PDFP-N. Item 11.10-412

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:

STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:

STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:

REGISTRATION - Thermally enhanced single in-line surface mount package. 21.50 mm Body Width, 1.40 mm Lead Pitch. R-PSIP-Fxx. Item 11.11-590.

STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:

Standard Practices and Procedures - Measuring Stand-off Heights of Packages

Registration - Plastic Quad Flatpack (PQFP) Outline with Exposed Heat Sink. Thermally Enhanced PQFPs. Addition of standard height, variations BA, BB, BC, BD, and BE with Exposed Heat Sink.

TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT:

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):

STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION):

Registration - Extremely Thin, Two Row Cavity Down, 0.50 mm Pitch BGA Family. The addition of -2, max matrix, variations to XFBGA. Item 11.11-604.

JEP95 Registrations Main Page

PROCEDURE FOR WAFER-LEVEL-TESTING OF THIN DIELECTRICS:

Registration - Plastic Small Outline Package with Exposed Heat Sink.

Registration - Square, Dual Pitch, FBGA Family. Item 11.11-581.

Registration - Bottom Terminal Ceramic Chip Carrier Family. Item 11.10-408.

Registration - Change the A4 dimension and value in the Plastic Small Outline Heatslug Package , 7.50 mm Body Wide, 1.0 mm Lead Pitch (H-PDSO-G). Item 11.11-589.

Registration - Plastic SOP, 13.30 mm Wide Body, 1.27 mm Pitch, with addition of a 90 lead Small Outline Package as variation CA. Item 11.11-571.

Standard - Low/Thin Profile Plastic Quad Flat Package, 2.00 mm Footprint, Optional Heat. Item 11.11-521S.

Registration - 144 Pin Small Outline Dual-In-Line Memory Module (DIMM) Family 0.8 mm Lead Centers with addition of optional beveled edge to SODIMM Family. Item 11.14-048.

GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING:

Registration - Addition of variations, BA, BB, BC, and BD, to Plastic, Surface Mounted Header Family. Item 11.10-406

Registration - Plastic Flange Mounted, 2 Lead, Power Package. Item 11.10-405

Registration - 232 Pin DDR SDRAM DIMM Family, 1.00 mm Pitch. Item 11.14-042

Registration - 210 Pin SDRAM Dual-In-Line Memory Module (DIMM) Family, 1.00 mm Contact Centers. Item 11.14-039. This Outline is Now Inactive. Item 11.14-047.

144 Pin SGRAM/SDRAM SO-DIMM Family

144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM

184 Pin DIMM Family Supplementary Design Standards

STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:

DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:

TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS:

Word Wide DRAM

TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS:

Design Requirements - Quad Flatpack

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