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Title	Document #	Date
REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES:	JEP104C.01	May 2003
This publication provides a quick reference to the letter symbols and corresponding terms that are defined in JESD77-B, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices; JESD99-A, Terms, Definitions, and Letter Symbols for Microelectronic Devices, and JESD100-B, Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits. It is intended to simplify interpretation of data sheets and specifications and to promote the uniform use of these symbols. The symbols relate to ratings and characteristics found in data sheets and other specifications. Some abbreviations used in lieu of symbols are also included. The newly added Annex B is provided as an aid to determining what symbol should be used and is organized by term, whereas the main body of the publication is organized by symbol or abbreviation as in previous versions. This version contains minor revisions Committee(s): JC-10 Free download. Registration or login required.
SPD Annex E, SDRAM	SPD4.1.2.5	May 2003
Release No. 12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Device Specification Annex for JESD21-C	SDRAM3.2	Apr 2003
Release No.12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Power Plastic Outline, Surface Mount with 1-Lead C-Bend Terminal. Includes Errata to DO-214, May 1998. Item 11.1-654(e).	DO-214-D	Apr 2003
Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
4.5 Table of Contents - Eight Byte Modules	MODULE4.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex A, Table of Memory Types	SPD4.1.2.1	Apr 2003
Release No.12 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SRAM	SRAM3.7.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM:	JEP145	Feb 2003
This publication is intended as a guideline to establish procedures, consideration and common practices that will allow a manufacturer, an application entity, a system designer and other interested parties to define current capability limitations in the leads of components and power systems with semiconductor components. This is a guideline, not a standardized method, it was developed over several years to clarify questions that had been posed to committee members in their respective engineering functions. Committee(s): JC-25 Free download. Registration or login required.
Registration - Stacked TSOP II Package Family (2 High). R-PDSO-G. Item 11.11-635	MO-238-A	Feb 2003
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic peripheral leaded, flange mounted package family with revision of lead dimensions (5 lead). R-PSFM-G. Item 11.10-423.	MO-235-B	Feb 2003
Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Mixed Pitch (0.80 & 1.00 mm), Rectangular Die Size, Fine Dual Pitch Ball Grid Array (DSBGA) family. TFR-XBGA-N. Item 11.4-611	MO-233-C	Feb 2003
Includes editorial correction of the ball array identification lettering (replace S with T). Item 11.1-652(E). Committee(s): JC-11, JC-11.4 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Addition of numerous N4 body sizes to variations AE and AF of Low Profile Matrix Tray for Handling and Shipping Thin Grid Array Devices Registration. Item 11.5-634.	CO-034-D	Feb 2003
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES: Removed 01/21/04 Release Number: B	J-STD-002	Feb 2003
At the request of IPC, J-STD-002B has been removed from the free download area. In its place, JEDEC's Test Method, JESD22-B102, Solderability, which includes lead-free, was made available until it was replaced by J-STD-002D. Any revision to J-STD-002 will no longer be available for free to the industry on the JEDEC website. However, the document is available to the JEDEC formulating Committee members, in the Members Area. If you are not a JEDEC member you may wish to try the IPC website or one of the resellers listed at: http://www.jedec.org/standards-document Committee(s): JC-13, JC-14.1
CONFIGURATIONS FOR SOLID STATE MEMORIES: Status: Under RevisionSections in this document may be under revision at any time.	JESD21-C	Jan 2003
This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003. Committee(s): JC-42 See JESD21-C information
Reinstated.	TO-059	Jan 2003
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 168 pin DIMM. Multiple Keyway Dual-In-Line Memory Module (DIMM), 1.27 mm contact centers. Addition of the 100 pin variation GA-XX and the INACTIVATION of the 168 pin right polarized configuration to DIMM registration. Item 11.14-055/056.	MO-161-F	Dec 2002
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS:	JESD100B.01	Dec 2002
A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors, microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and their definitions in this standard have been updated and are in general agreement with the latest publications of the IEEE and the IEC. The companion standard for other integrated circuits is JESD99A. Also included is a system for generating symbols for time intervals found in complex sequential circuits, including memories. JESD100B.01 is the first minor revision of JESD100-B, December 1999. Annex A briefly shows entries that have changed. Committee(s): JC-10 Free download. Registration or login required.
Registration - Thermally Enhanced Plastic Very Thin Dual Row Fine Pitch Quad Flat No Lead Package. HP-VFQFP-N. Item 11.11-680	MO-239-B	Nov 2002
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Thin Matrix Tray for Shipping and Handling of Ball Grid Packages. Includes Change to Note 18. Item 11.5-633	CO-029-H	Sep 2002
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.	MO-214-B	Sep 2002
0.50 mm Lead Centers Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION	JESD82-5	Jul 2002
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required.
BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES Status: ReaffirmedJune 2006, September 2011, January 2015	JEP140	Jun 2002
The beaded thermocouple temperature measurement guideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications can include, but not limited to, temperature profile measurement in reliability test chambers and solder reflow operations that are associated with component assembly to printed wiring boards. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
General SDRAM Functions	SDRAM3.11.5.1	Jun 2002
Release No. 12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - The general update and change of lead dimensions for flange mounted family, insertion mount (peripheral terminals). R-PSIP-F3. Item 11.10-417	TO-251-D	Jun 2002
Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002.	JESD8-9B	May 2002
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. Committee(s): JC-16 Free download. Registration or login required.
Registration - Dimensional update and removal of land pattern from the SOP/SOT registration. R-PDSO-G. Item 11.10-416	TO-261-C	May 2002
Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
OUTLIER IDENTIFICATION AND MANAGEMENT SYSTEM FOR ELECTRONIC COMPONENTS, RESCINDED January 2009. Replaced by JESD50. Status: RescindedJanuary 2009	JESD62-A	May 2002
Relevant JESD62 content has been consolidated into JESD50B, published October 2008 -Special Requirments for Maverick Product Elimination-. Committee(s): JC-14.3 Free download. Registration or login required.
Registration - The addition of 47.5, 50.0, 52.5 and 55.0 mm body variations with 1.27 mm and 1.00 mm ball pitch to Column Grid Array Registration. Item 11.10-415. CBGA-X/CCBA	MO-158-D	Apr 2002
Patents(): IBM: 4,914,814 Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Consolidation and addition of numerous variations to the thermally enhanced plastic very thin fine pitch quad flat, no lead package. HP-VFQFP-N/HP-WFQFP-N. Item 11.11-620. This document is being removed based on decission by the Chair under directive from the BoD, letter is attached	MO-220-D	Feb 2002
This registration has been removed. Please 'open file' for more information regarding this issue. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:	JESD28-A	Dec 2001
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:	JESD73-3	Nov 2001
This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Committee(s): JC-40, JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:	JESD73-4	Nov 2001
This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Committee(s): JC-40, JC-40.2 Free download. Registration or login required.
Registration - Very Very Thin Quad Bottom Terminal Chip Carrier Family with Addition of variations AE, AF, AG, BE, BF, and BG. W-PBCC-B/WH-PBCC-B. Item 11.11-621.	MO-217-B	Nov 2001
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Thin Fine Pitch Quad Flat, No Lead, Package. Registration of Quad, Single and Double Row SON Packages. The addition of 7 new thermal variations. Item 11.11-599.	MO-208-C	Nov 2001
Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Module Introduction	MODULE4	Oct 2001
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Standard Template for JEDEC Module Standards	MODULE4.20.1	Oct 2001
Release No. 11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:	JESD75-1	Oct 2001
This standard establishes a 54 Ball Grid Array pinout for 16, 18 and 20-bit standard logic devices that are currently being produced in 48 and 56 Pin SSOP and TSSOP packages. The 54 Ball Grid Array Package is organized as a 6 x 9 array with balls on a .8mm x .8mm grid pitch. Committee(s): JC-40 Free download. Registration or login required.
SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400):	JESD8-13	Oct 2001
This standard defines the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nominally between 0 and 400 mV. Power supplies other than the nominal 800 mV power for the SLVS interface are not specified. Committee(s): JC-16 Free download. Registration or login required.
168 Pin Registered SDRAM DIMM Family	MODULE4.5.7	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin SDRAM DIMM	MODULE4.5.2	Oct 2001
Release No.11 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

REFERENCE GUIDE TO LETTER SYMBOLS FOR SEMICONDUCTOR DEVICES:

SPD Annex E, SDRAM

Device Specification Annex for JESD21-C

Registration - Power Plastic Outline, Surface Mount with 1-Lead C-Bend Terminal. Includes Errata to DO-214, May 1998. Item 11.1-654(e).

4.5 Table of Contents - Eight Byte Modules

SPD Annex A, Table of Memory Types

Byte Wide SRAM

GUIDELINE FOR ASSESSING THE CURRENT-CARRYING CAPABILITY OF THE LEADS IN A POWER PACKAGE SYSTEM:

Registration - Stacked TSOP II Package Family (2 High). R-PDSO-G. Item 11.11-635

Registration - Plastic peripheral leaded, flange mounted package family with revision of lead dimensions (5 lead). R-PSFM-G. Item 11.10-423.

Registration - Mixed Pitch (0.80 & 1.00 mm), Rectangular Die Size, Fine Dual Pitch Ball Grid Array (DSBGA) family. TFR-XBGA-N. Item 11.4-611

Registration - Addition of numerous N4 body sizes to variations AE and AF of Low Profile Matrix Tray for Handling and Shipping Thin Grid Array Devices Registration. Item 11.5-634.

SOLDERABILITY TESTS FOR COMPONENT LEADS, TERMINATIONS, LUGS, TERMINALS AND WIRES:

CONFIGURATIONS FOR SOLID STATE MEMORIES:

Reinstated.

Registration - 168 pin DIMM. Multiple Keyway Dual-In-Line Memory Module (DIMM), 1.27 mm contact centers. Addition of the 100 pin variation GA-XX and the INACTIVATION of the 168 pin right polarized configuration to DIMM registration. Item 11.14-055/056.

TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS:

Registration - Thermally Enhanced Plastic Very Thin Dual Row Fine Pitch Quad Flat No Lead Package. HP-VFQFP-N. Item 11.11-680

Registration - Thin Matrix Tray for Shipping and Handling of Ball Grid Packages. Includes Change to Note 18. Item 11.5-633

Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.

STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGES

General SDRAM Functions

Registration - The general update and change of lead dimensions for flange mounted family, insertion mount (peripheral terminals). R-PSIP-F3. Item 11.10-417

ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002.

Registration - Dimensional update and removal of land pattern from the SOP/SOT registration. R-PDSO-G. Item 11.10-416

OUTLIER IDENTIFICATION AND MANAGEMENT SYSTEM FOR ELECTRONIC COMPONENTS, RESCINDED January 2009. Replaced by JESD50.

Registration - The addition of 47.5, 50.0, 52.5 and 55.0 mm body variations with 1.27 mm and 1.00 mm ball pitch to Column Grid Array Registration. Item 11.10-415. CBGA-X/CCBA

Registration - Consolidation and addition of numerous variations to the thermally enhanced plastic very thin fine pitch quad flat, no lead package. HP-VFQFP-N/HP-WFQFP-N. Item 11.11-620.

A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:

STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:

STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:

Registration - Very Very Thin Quad Bottom Terminal Chip Carrier Family with Addition of variations AE, AF, AG, BE, BF, and BG. W-PBCC-B/WH-PBCC-B. Item 11.11-621.

Registration - Plastic Thin Fine Pitch Quad Flat, No Lead, Package. Registration of Quad, Single and Double Row SON Packages. The addition of 7 new thermal variations. Item 11.11-599.

Module Introduction

Standard Template for JEDEC Module Standards

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:

SCALABLE LOW-VOLTAGE SIGNALING FOR 400 MV (SLVS-400):

168 Pin Registered SDRAM DIMM Family

200 Pin SDRAM DIMM

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