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Title	Document #	Date
Design Requirements - Micropillar Grid Array (MPGA)	DR-4.26B	Nov 2015
Item 11.2-845(R) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES Status: Reaffirmed September 2021	JESD241	Dec 2015
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.2 Free download. Registration or login required.
Registration - 6 Lead Surface Mount Power Package with Fused Leads. H-PSOF	MO-319A	Feb 2016
Item No. 11-912 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Annex J, Raw Card J, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification Release Number: 26	MODULE4.20.28.J	Feb 2016
Item 2241.16 This specification defines the electrical and mechanical requirements for Raw Card J, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Universal Flash Storage (UFS), Version 2.1 Status: Superseded August 2020	JESD220C-2.1	Mar 2016
This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model is referencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10 (SCSI) SPC and SBC standards. Item 133.00B A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 2.1 Status: Supersededby JESD223D, January 2018	JESD223C	Mar 2016
This document has been superseded by JESD223D, January 2018, however is available for reference only. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS) UNIFIED MEMORY EXTENSION, Version 1.1	JESD220-1A	Mar 2016
This UFS Unified Memory Support Extension standard is an extension to the UFS standard, JESD220, This standard defines a managed storage device. UFS devices are designed to offer a high performance with low power consumption. The UFS device contains features that support both high throughput for large data transfers and performance for small random data accesses. This standard describes the requirements to implement unified memory functionality in an UFS device. Unified Memory Support is not mandatory but optional. Item 133.11 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
Registration - DDR4 DIMM PTH 288 Pin Socket Outline, 0.85 mm Pitch. SKT	SO-016C.01	Apr 2016
Item No. 14-181(E) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 DIMM SMT, 288 Pin Socket Outline, 0.85 mm Pitch. SKT	SO-017C.01	Apr 2016
Item No. 14-181(E) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
REGISTRATION - DDR4 DIMM Press Fit 288 Pin Socket Outline, 0.85 mm Pitch. SKT	SO-019C.01	Apr 2016
Item 14-181(E) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), UNIFIED MEMORY EXTENSION, Version 1.1A	JESD223-1B	May 2016
This Unified Memory Extension standard is an extension to the UFSHCI standard, JESD223. The UFSHCI standard defines the interface between the UFS driver and the UFS host controller. In addition to the register interface, it defines data structures inside the system memory, which are used to exchange data, control and status information. Furthermore the UFSHCI standard defines the protocol layer structure and abstract entities within these layers. Unified Memory offers the possibility to move Device internal working memory into the system memory to reduce overall system cost and to improve Device performance. Item 203.25 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
Annex C, Raw Card C, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30	MODULE4.20.26.C	Jun 2016
This annex defines the electrical and mechanical requirements for Raw Card C, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.37 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex B, Raw Card B, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SO-DIMM Design Specification Release Number: 26	MODULE4.20.25.B	Jun 2016
This annex defines the electrical and mechanical requirements for Raw Card B, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item no. 2228.17A A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
MULTI-WIRE MULTI-LEVEL I/O STANDARD	JESD247	Jun 2016
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-16 Free download. Registration or login required.
DDR4 260 Pin SODIMM Connector Performance Standard	PS-003A.01	Jul 2016
This standard defines the form, fit and function of SODIMM DDR4 connectors for modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR4 connectors in client and server platforms. Item 11.14-179E A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 288 PIN DDR4 MINI DIMM, 0.50 MM PITCH	MO-314A.02	Jul 2016
Item 14-183, Minor Editorial Revision A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
SOLDER BALL PULL Status: Reaffirmed September 2021	JESD22-B115A.01	Jul 2016
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS	J-STD-046	Jul 2016
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.4 Free download. Registration or login required.
Registration - 12 Pin UFS Socket Outline, 0.91 mm Pitch. SKT	SO-022A	Aug 2016
Item No. 14-182 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.80 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-326A	Aug 2016
Item No. 11-928 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.65 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-325A	Aug 2016
Item No. 11-927 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.50 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-324A	Aug 2016
Item No. 11-926 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, SQUARE, 0.40 mm Top, 0.40 mm Bottom Pitch. S-XBGA.	MO-302C	Aug 2016
Item No.11-930 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)	DG-4.25B	Aug 2016
This Design Requirement defines the symbols, definitions, algorithms, and specified dimensions and tolerances for Fine-pitch, LGA packages. The guidelines defined are based on hard metric dimensions and adhere to the geometric dimensioning and tolerancing principles defined in ASME Y14.5M-1994. Item 11.2-896(S) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)	DG-4.24B	Aug 2016
Item 11.2-850(S) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 9 Lead Surface Mount Power Package, 1.2 mm Pitch. H-PSOF	MO-327A	Sep 2016
Item No. 11-925 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).	DG-4.20F	Sep 2016
Item 11.2-820(S) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
UNDERSTANDING ELECTRICAL OVERSTRESS - EOS Status: Reaffirmed May 2022	JEP174	Sep 2016
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.3 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
VIBRATION, VARIABLE FREQUENCY	JESD22-B103B.01	Sep 2016
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.1 Free download. Registration or login required.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification Status: RescindedThis document is published as JESD248Release Number: 26	MODULE4.20.29	Oct 2016
See JESD248 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-45.6 JESD21-C Solid State Memory Documents Main Page
UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSION Item 112.99	JESD225	Nov 2016
This document provides a comprehensive definition of the UFS security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
EMBEDDED MULTIMEDIACARD (e•MMC) SECURITY EXTENSION Item 65.02	JESD227	Nov 2016
This document provides a comprehensive definition of the e•MMC Security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-64.1 Free download. Registration or login required.
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES Status: Reaffirmed February 2023	JESD22-B106E	Nov 2016
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.1 Free download. Registration or login required.
0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)	JESD8-29	Dec 2016
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-16 Free download. Registration or login required.
Registration - Ball Grid Array Family, Square, 1.00 mm Pitch. PBGA	MO-318B	Jan 2017
Item 11.11-934 Outline Cross Reference: Design Registration 4.14 (DR4.14) A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - Ball Grid Array Family, Square, 1.27 mm, and 1.50 mm Pitch. S-PBGA/PBGA.	MS-034G	Jan 2017
Item No. 11.11-933 (S) Item No. 11.11-723(S), Elevated MO-151 to Standard and included and increased Ax dimensions to allow for thicker packages. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
LEAD INTEGRITY Status: Reaffirmed - May 2023	JESD22-B105E	Feb 2017
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Registration - Flange Mounted Family, Surface Mount, Peripheral Terminals. R-PSFM-G.	TO-252F	Feb 2017
Item 11.10-456 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORS	JESD210A	Mar 2017
This standard is applicable to avalanche breakdown diodes when used as a surge protector or transient voltage suppressor (TVS). It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. This standard may be applied to other surge-protection components with similar characteristics as the ABD. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-22.2, JC-22.5 Free download. Registration or login required.

Standards & Documents Search

Design Requirements - Micropillar Grid Array (MPGA)

PROCEDURE FOR WAFER-LEVEL DC CHARACTERIZATION OF BIAS TEMPERATURE INSTABILITIES

Registration - 6 Lead Surface Mount Power Package with Fused Leads. H-PSOF

Annex J, Raw Card J, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

Universal Flash Storage (UFS), Version 2.1

UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 2.1

UNIVERSAL FLASH STORAGE (UFS) UNIFIED MEMORY EXTENSION, Version 1.1

Registration - DDR4 DIMM PTH 288 Pin Socket Outline, 0.85 mm Pitch. SKT

Registration - DDR4 DIMM SMT, 288 Pin Socket Outline, 0.85 mm Pitch. SKT

REGISTRATION - DDR4 DIMM Press Fit 288 Pin Socket Outline, 0.85 mm Pitch. SKT

UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), UNIFIED MEMORY EXTENSION, Version 1.1A

Annex C, Raw Card C, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification

Annex B, Raw Card B, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SO-DIMM Design Specification

MULTI-WIRE MULTI-LEVEL I/O STANDARD

DDR4 260 Pin SODIMM Connector Performance Standard

Registration - 288 PIN DDR4 MINI DIMM, 0.50 MM PITCH

SOLDER BALL PULL

CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS

Registration - 12 Pin UFS Socket Outline, 0.91 mm Pitch. SKT

Registration - Lower PoP Ball Grid Array Family, Square, 0.80 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - Lower PoP Ball Grid Array Family, Square, 0.65 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - Lower PoP Ball Grid Array Family, Square, 0.50 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - Lower PoP Ball Grid Array Family, SQUARE, 0.40 mm Top, 0.40 mm Bottom Pitch. S-XBGA.

Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)

Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)

Registration - 9 Lead Surface Mount Power Package, 1.2 mm Pitch. H-PSOF

Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).

UNDERSTANDING ELECTRICAL OVERSTRESS - EOS

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

VIBRATION, VARIABLE FREQUENCY

288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification

UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSION

EMBEDDED MULTIMEDIACARD (e•MMC) SECURITY EXTENSION

RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES

0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)

Registration - Ball Grid Array Family, Square, 1.00 mm Pitch. PBGA

Standard - Ball Grid Array Family, Square, 1.27 mm, and 1.50 mm Pitch. S-PBGA/PBGA.

LEAD INTEGRITY

Registration - Flange Mounted Family, Surface Mount, Peripheral Terminals. R-PSFM-G.

AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORS

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