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UNIVERSAL FLASH STORAGE, Version 4.0

Status: Superseded December 2024 by JESD220G 		JESD220F Aug 2022

NOTE: This document has been superseded by JESD220G published in December 2024, but remains available for reference purposes.

 

Committee(s): JC-64.1

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UNIVERSAL FLASH STORAGE, UFS 2.2

 JESD220C-2.2 Aug 2020

The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster.  Item 138.88.

Committee(s): JC-64.1

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Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0

Status: Superseded December 2024 by JESD223F 		JESD223E Aug 2022

NOTE: This document has been superseded by JESD223F published in December 2024, but remains available for reference purposes.

Committee(s): JC-64.1

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UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 3.0

Status: Superseded August 2022 by JESD223E 		JESD223D Jan 2018

This document has been superseded by JESD223E, however it is available for reference only.

Committee(s): JC-64.1

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UNIVERSAL FLASH STORAGE HOST CONTROLLER INTERFACE (UFSHCI), Version 2.1

Status: Supersededby JESD223D, January 2018 		JESD223C Mar 2016

This document has been superseded by JESD223D, January 2018, however is available for reference only.

Committee(s): JC-64.1

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Universal Flash Storage Host Controller Interface (UFSHCI)

Release Number: Version 4.1 		JESD223F Dec 2024

This document replaces all prior versions; however, JESD223E August 2022 (version 4.0) remains available for reference purposes.

This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY].

Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI.

Committee(s): JC-64, JC-64.1

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UNIVERSAL FLASH STORAGE (UFS), Version 3.1

 JESD220E Jan 2020

This document has been superseded by JESD220F, August 2022, however is available for reference only.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64.1

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UNIVERSAL FLASH STORAGE (UFS), Version 3.0

Status: Superseded January 2020 		JESD220D Jan 2018

This document has been superseded by JESD220E, January 2020, however is available for reference only.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-64.1

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Universal Flash Storage (UFS), Version 2.1

Status: Superseded August 2020 		JESD220C-2.1 Mar 2016

This document has been superseded by JESD220C-2.2, August 2020, and is provided here for reference purposes only.

This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. The architectural model is referencing the INCITS T10 (SCSI) SAM standard and the command protocol is based on INCITS T10 (SCSI) SPC and SBC standards. Item 133.00B

Committee(s): JC-64.1

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Universal Flash Storage (UFS)

Release Number: Version 4.1 		JESD220G Dec 2024

This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes.

This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device.

Committee(s): JC-64, JC-64.1

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STANDARD MANUFACTURERS IDENTIFICATION CODE

 JEP106BK Sep 2024

The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form

Committee(s): JC-42, JC-42.3

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SPD General Standard.

 SPD4.1.2 Jul 2008

Release No. 19. Item 2065.26

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

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SPD Annex J: Serial Presence Detect for DDR2 SDRAM

 SPD4.1.2.10 Jan 2007

Release No. 17

Committee(s): JC-42, JC-45

JESD21-C Solid State Memory Documents Main Page

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SPD Annex F, Address Multiplexed ROM

 SPD4.1.2.6 Jun 1998

Release No.8

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)

 SPD4.1.2.4 Jan 2004

Release No.13

Committee(s): JC-42, JC-42.5

JESD21-C Solid State Memory Documents Main Page

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SPD Annex C, Fast Page and Extended Data Out RAM

 SPD4.1.2.3 Jan 1998

Release No.8

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

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Serial Flash Discoverable Parameters (SFDP)

 JESD216G Nov 2024

The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data.

Committee(s): JC-42.4

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RADIO FRONT END - BASEBAND (RF-BB) INTERFACE

 JESD96A.01 Mar 2023

Terminology update.  

This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

Committee(s): JC-61

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LPDDR5/5X Serial Presence Detect (SPD) Contents

Release Number: 1.0 		JESD406-5A Nov 2024

This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding.

Committee(s): JC-45

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JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

Release Number: 1.1 		JESD405-1B Jun 2024

This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format.

Committee(s): JC-45

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