Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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ACCELERATED MOISTURE RESISTANCE - UNBIASED HAST |
JESD22-A118B.01 | May 2021 |
The Unbiased HAST is performed for the purpose of evaluating the reliability of nonhermetic packaged solid-state devices in humid environments. It is a highly accelerated test which employs temperature and humidity under noncondensing conditions to accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be uncovered (e.g., galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.1 Free download. Registration or login required. |
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ACCEPTED PRACTICES FOR MAKING MICROELECTRONIC DEVICE THERMAL CHARACTERISTICS TESTSStatus: Rescinded |
JEB20 | Jan 1975 |
A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11 |
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ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES |
JEP176 | Jan 2018 |
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.3 Free download. Registration or login required. |
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ADDENDUM No. 1 to EIA-318 - CHARACTERIZATION OF A REVERSE TEST FIXTURE: SUPERSEDED BY EIA-318-B, July 1996.Status: Rescinded |
EIA318-1 | Feb 1981 |
A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-22.4 Free download. Registration or login required. |
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ADDENDUM No. 1 TO EIA-397: |
EIA397-1 | Jul 1980 |
A compilation of 12 new or revised thyristor test methods which have been adopted since the original standard was issued in 1972. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-22.1 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD12 - TERMS AND DEFINITIONS FOR GATE ARRAYS AND CELL-BASED INTEGRATED CIRCUITS: |
JESD12-1B | Aug 1993 |
The purpose of this standard is to promote the uniform use of abbreviations, terms, and definitions throughout the semiconductor industry. It is a useful guide for users, manufactures, educators, technical writers, and others interested in the characterization, nomenclature, and classification of semicustom integrated circuits. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-44 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD209-4, LOW POWER DOUBLE DATA RATE 4X (LPDDR4X) |
JESD209-4-1A | Feb 2021 |
This addendum defines LPDDR4X specifications that supersede the LPDDR4 Standard (JESD209-4) to enable low VDDQ operation of LPDDR4X devices to reduce power consumption. Item 1831.55A. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $106.00 Add to Cart Paying JEDEC Members may login for free access. |
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Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O. |
JESD209A-1 | Mar 2009 |
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD24 - METHOD FOR MEASUREMENT OF POWER DEVICE TURN-OFF SWITCHING LOSS:Status: ReaffirmedApril 1999, October 2002 |
JESD24- 1 | Oct 1989 |
Describes the method of a typical oscilloscope waveform and the basic test circuit employed in the measurement of turn off loss for bipolar, IGBT and MOSFET power semiconductors. This method can be used as a standard for evaluating power semiconductor turn-off switching loss capability and defines standard terminology that should be referenced within the electronic industry. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-25 Free download. Registration or login required. |
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Addendum No. 1 to JESD251 - OPTIONAL x4 QUAD I/O WITH DATA STROBE |
JESD251-1.01 | Sep 2021 |
This purpose of the addendum is to add an optional 4-bit bus width (x4) to JESD251, xSPI standard. The xSPI interface currently supports a x1 interface that acts as a bridge to legacy SPI functionality as well as the x8 interface intended to achieve dramatically higher bus performance than legacy SPI memory implementations. Item 1775.15. This is an editorial revision to JESD251-1, October 2018 A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-42.4 Free download. Registration or login required. |
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Addendum No. 1 to JESD28, N-CHANNEL MOSFET HOT CARRIER DATA ANALYSIS |
JESD28-1 | Sep 2001 |
This addendum provides data analysis examples useful in analyzing MOSFET n-channel hot-carrier-induced degradation data. This addendum to JESD28 (Hot carrier n-channel testing standard) suggests hot-carrier data analysis techniques. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.2 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD35, GENERAL GUIDELINES FOR DESIGNING TEST STRUCTURES FOR THE WAFER-LEVEL TESTING OF THIN DIELECTRICSStatus: Rescinded |
JESD35-1 | Sep 1995 |
JESD35-1 was rescinded by the committee in June 2024 and has been superseded by JESD263. This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.2 |
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Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866This is a minor editorial revision, the differences between revisions can be found on page 17 of the document. |
JESD79-3-1A.01 | May 2013 |
The JESD79-3 document defines DDR3L SDRAM, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments with the exception of what is stated within this standard. The purpose of this standard is to define the DDR3L specifications that supersede the DDR3 specifications as defined in JESD79-3. The use of DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600, and DDR3L-1866 titles in JESD79-3 are to be interpreted as DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866 respectively, when applying towards DDR3L definition; unless specifically stated otherwise. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Free download. Registration or login required. |
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Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1B | Feb 2021 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD8: INTERFACE STANDARD FOR LOW VOLTAGE TTL-COMPATIBLE (LVTTL) VLSI DIGITAL CIRCUITSStatus: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999. |
JESD8-1 | Jun 1994 |
A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-16 Free download. Registration or login required. |
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Addendum No. 1 to JESD96A - INTEROPERABILITY AND COMPLIANCE TECHNICAL REQUIREMENTS FOR JEDEC STANDARD JESD96A - RECOMMENDED PRACTICE FOR USE WITH IEEE 802.11N |
JESD96A-1 | Jan 2007 |
The normative information in this publication is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), when designed to JESD96A. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-61 Free download. Registration or login required. |
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ADDENDUM No. 1 to JESD99, TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERSStatus: Incorporated into JESD99-A, May 2000 |
JESD99-1 | Jul 1989 |
This addendum has now been incorporated into JESD99. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-10 Free download. Registration or login required. |
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ADDENDUM No. 10 to JESD24 - TEST METHOD FOR MEASUREMENT OF REVERSE RECOVERY TIME trr FOR POWER MOSFET DRAIN-SOURCE DIODES:Status: ReaffirmedOctober 2002 |
JESD24-10 | Aug 1994 |
Test method to measure the reverse recovery characteristics of the drain source diode of a power MOSFET. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 11 to JESD24 - POWER MOSFET EQUIVALENT SERIES GATE RESISTANCE TEST METHOD:Status: ReaffirmedMarch 2001, October 2002 |
JESD24-11 | Aug 1996 |
Test method to measure the equivalent resistance of the gate to source of a power MOSFET. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 11A.01 to JESD8 - 1.5 V +/- 0.1 V (NORMAL RANGE) AND 0.9 - 1.6 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS: |
JESD8-11A.01 | Sep 2007 |
This new standard provides specifications that will be used by several companies in new 1.5 V products designed in 0.12-0.15 um CMOS technologies, and in components that interface with them. The specifications allow limited interoperability with products using the existing JEDEC HSTL specification (JESD8-6). This version is a minor editorial revision as noted in Annex A. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-16 Free download. Registration or login required. |
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