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Title	Document #	Date
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification Status: RescindedThis document is published as JESD248Release Number: 26	MODULE4.20.29	Oct 2016
See JESD248 Committee(s): JC-45.6 JESD21-C Solid State Memory Documents Main Page
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 25	MODULE4.20.27	Aug 2015
Item 2204.07 This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification Release Number: 29	MODULE4.20.28	May 2019
This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Item 2149.05E Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
300 mV INTERFACE	JESD8-28	Jun 2015
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. Committee(s): JC-16 Free download. Registration or login required.
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions	JEP158	Nov 2009
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
4.5 Table of Contents - Eight Byte Modules	MODULE4.5	Apr 2003
Release No.12 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
4.6 Table of Contents - Sixteen Byte Modules	MODULE4.6	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
48 Lead, Very, Very Thin Small Outline Package, Type 1. WR-PDSO1, WSOP1. Item 11.11-701.	MO-259-A	Mar 2005
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
64 & 72 Pin ZIP/SIMM SRAM Module	MODULE4.4.1	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SIMM	MODULE4.4.2	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SO-DIMM	MODULE4.4.4	Jun 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
80 Pin EEPROM SIMM	MODULE4.4.7	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
88 Pin DRAM Card Status: Reaffirmed	MODULE4.4.3	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
88 Pin DRAM SO-DIMM	MODULE4.4.5	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces	JEP196	Nov 2023
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
A PROCEDURE FOR EXECUTING SWEAT: Status: Reaffirmed October 2012, September 2018	JEP119A	Aug 2003
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION UNDER DC STRESS:	JESD28-A	Dec 2001
This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS:	JESD60A	Sep 2004
This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET NEGATIVE BIAS TEMPERATURE INSTABILITIES Status: Rescinded September 2021 (JC-14.2-21-183)	JESD90	Nov 2004
This document hasbeen replaced by JESD241, September 2021. Committee(s): JC-14, JC-14.2
ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE Status: Reaffirmed January 2021	JESD22-A102E	Jul 2015
This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test that employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules