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Title	Document #	Date
Performance Standard - DDR4 288 Pin U/R/LR DIMM Connector Performance Standard	PS-002A	Jul 2015
This standard defines the form, fit and function of DDR4 connectors for U/R/LR modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.40 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR4 connectors in client and server platforms. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY	JEP159A	Jul 2015
This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
300 mV INTERFACE	JESD8-28	Jun 2015
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. Committee(s): JC-16 Free download. Registration or login required.
Annex G, R/C G, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification Release Number: 25	MODULE4.20.28.G	Jun 2015
Item 2241.06B This specification defines the electrical and mechanical requirements for Raw Card G, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM	MO-309F	Mar 2015
Item No. 11.14-176 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - mSATA SSD Assembly. DIM.	MO-300C	Mar 2015
Item 11.14-175 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 MiniDIMM SMT 288 pin socket outline 0.50 mm pitch	SO-021A	Feb 2015
Item No. 11.14-174 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual Pitch Number Ball Grid Array Family, Square, 0.80 mm Major, 0.65 mm Minor Pitch. (T,V)F-SBGA	MO-315A	Feb 2015
Item No. 11-903 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Surface Mount Power Package with fused leads. H-PSOF	MO-299B	Jan 2015
Item 11.11-902 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Small Outline, Wide Body SOIC, 7.5 Body Width, 0.65 Pitch. R-PDSO.	MO-286B	Jan 2015
Item 11.10-450 Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Dual Inline Memory Modules (DIMMs) Table of Contents	MODULE4.20.TOC	Dec 2014
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE	J-STD-048	Nov 2014
This document supersedes JESD48. This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. The goal of this notification standard is to better enable customers to manage and mitigate the disruption caused by the discontinuation of a product and ensure continuity of supply. This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition ongoing requirements to alternate products. Committee(s): JC-14.4 Free download. Registration or login required.
Standard Practices and Procedures - Registered and Standard Outlines	SPP-013A	Oct 2014
Item 11.2-886(E). This document has been editorially updated to provide template examples. Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM	MO-274D	Oct 2014
Item 11.14-171 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
WIDE I/O 2 (WideIO2)	JESD229-2	Aug 2014
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required.
GDDR5 MEASUREMENT PROCEDURES	JEP171	Aug 2014
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s): JC-42.3 Free download. Registration or login required.
Annex F, R/C F, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification Release Number: 24	MODULE4.20.25.F	Aug 2014
Item 2228.02 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Fine Pitch Ball Grid Array Family, Square, 0.50 mm pitch. (T, V) F-SBGA	MO-313A	Aug 2014
Item No. 11-892 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Grid Array Terminal Position Numbering	SPP-010B	May 2014
Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
SOLDER BALL SHEAR Status: Reaffirmed September 2020	JESD22-B117B	May 2014
The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball shear is a destructive test. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.

Standards & Documents Search

Performance Standard - DDR4 288 Pin U/R/LR DIMM Connector Performance Standard

PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

300 mV INTERFACE

Annex G, R/C G, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM

Registration - mSATA SSD Assembly. DIM.

Registration - DDR4 MiniDIMM SMT 288 pin socket outline 0.50 mm pitch

Registration - Dual Pitch Number Ball Grid Array Family, Square, 0.80 mm Major, 0.65 mm Minor Pitch. (T,V)F-SBGA

Registration - Surface Mount Power Package with fused leads. H-PSOF

Registration - Plastic Small Outline, Wide Body SOIC, 7.5 Body Width, 0.65 Pitch. R-PDSO.

Dual Inline Memory Modules (DIMMs) Table of Contents

JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE

Standard Practices and Procedures - Registered and Standard Outlines

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM

WIDE I/O 2 (WideIO2)

GDDR5 MEASUREMENT PROCEDURES

Annex F, R/C F, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification

Registration - Fine Pitch Ball Grid Array Family, Square, 0.50 mm pitch. (T, V) F-SBGA

Standard Practices and Procedures - Grid Array Terminal Position Numbering

SOLDER BALL SHEAR

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