Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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Information Requirements for the Qualification of Solid State Devices |
JESD69D | Jun 2024 |
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Free download. Registration or login required. |
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INSPECTION CRITERIA FOR MICROELECTRONIC PACKAGES AND COVERSStatus: Reaffirmed May 2023 |
JESD9C | May 2017 |
The purpose of this JEDEC standard is to verify the workmanship and requirements of microelectronic packages and covers (lids) intended for use in fabricating hybrid microelectronic circuits/microcircuits (hereafter referred to as “microcircuits”). It is applicable for use by the package manufacturer (i.e., package components), and the microcircuit manufacturer (i.e., from incoming inspection of package components through final inspection of the completed microcircuit). This standard also encompasses and replaces JESD27, Ceramic Package Specification for Microelectronic Packages. It is meant to be used in conjunction, and to not contradict, with MIL-STD-883, Test Method 2009: External Visual. Free download. Registration or login required. |
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INSTRUMENTATION CHIP DATA SHEET FOR FBDIMM DIAGNOSTIC SENSELINES |
JESD82-22.01 | Feb 2023 |
Terminology update. Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL MEASUREMENT METHOD - ELECTRICAL TEST METHOD (SINGLE SEMICONDUCTOR DEVICE): |
JESD51- 1 | Dec 1995 |
The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. This method will provide a basis for comparison of different devices housed in the same electronic package or similar devices housed in different electronic packages. Committee(s): JC-15.1 Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR): |
JESD51- 6 | Mar 1999 |
This standard specifies the environmental conditions for determining thermal performance of an integrated circuit device in a forced convection environment when mounted on a standard thermal test board. Committee(s): JC-15.1 Free download. Registration or login required. |
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INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - JUNCTION-TO-BOARD: |
JESD51- 8 | Oct 1999 |
This specification should be used in conjunction with the overview document JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) [1] and the electrical test procedures described in JESD51-1, 'Integrated Circuit Thermal Measurement Method (Single Semiconductor Device' [2. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paths to the printed board caused by such thermal enhancements as fused leads (leads connected to the die pad) or power style packages with the exposed heat slug on one side of the package. Committee(s): JC-15.1 Free download. Registration or login required. |
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INTEGRATED CIRCUITS THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - NATURAL CONVECTION (STILL AIR) |
JESD51-2A | Jan 2007 |
This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection. Committee(s): JC-15.1 Free download. Registration or login required. |
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INTERFACE STANDARD FOR NOMINAL 0.3 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITSStatus: Incorporatedinto JESD8-A, June 1994. JESD8-A was replaced by JESD8-B, September 1999. |
JESD8-1A | Jun 1994 |
Committee(s): JC-16 Free download. Registration or login required. |
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INTERFACE STANDARD FOR NOMINAL 3.0 V/3.3 V SUPPLY DIGITAL INTEGRATED CIRCUITS: |
JESD8C.01 | Sep 2007 |
This standard (a replacement of JEDEC Standards No. 8, 8-1, 8-1-A, and 8-A) defines dc interface parameters for a family of digital circuits operating from a power supply of nominal 3.0 V/3.3. V and driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for LVTTL-compatible and LVCMOS-compatible circuits. Committee(s): JC-16 Free download. Registration or login required. |
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IPC/JEDEC-9702: MONOTONIC BEND CHARACTERIZATION OF BOARD-LEVEL INTERCONNECTS (IPC/JEDEC-9702) |
JS9702 | Jun 2004 |
This publication specifies a common method of establishing the fracture resistance of board-level device interconnects to flexural loading during non-cyclic board assembly and test operations. Monotonic bend test qualification pass/fail requirements are typically specific to each device application and are outside the scope of this document. This version contains Addendum 1, May 2015, reposted 8/15/2016. Committee(s): JC-14.1 Free download. Registration or login required. |
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IPC/JEDEC-9703: MECHANICAL SHOCK TEST GUIDELINE FOR SOLDER JOINT RELIABILITYStatus: Reaffirmed May 2014, May 2019 |
JS9703 | Mar 2009 |
This document establishes mechanical shock test guidelines for assessing solder joint reliability of Printed Circuit Board (PCB) assemblies from system to component level. Committee(s): JC-14.1 Free download. Registration or login required. |
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IPC/JEDEC-9704A: PRINTED WIRING BOARD (PWB) STRAIN GAGE TEST GUIDELINE |
JS9704A | Jan 2012 |
This document describes specific guidelines for strain gage testing for Printed Wiring Board (PWB)assemblies. The suggested procedures enables board manufacturers to conduct required strain gage testing independently, and provides a quantitative method for measuring board flexure, and assessing risk levels. The topics covered include: Test setup and equipment; requirements; Strain measurement; Report format Free download. Registration or login required. |
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ISOTHERMAL ELECTROMIGRATION TEST PROCEDURE:Status: Reaffirmed September 2018 |
JESD61A.01 | Oct 2007 |
This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test. Free download. Registration or login required. |
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JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES |
JEP166E | Jul 2023 |
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required. |
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JEDEC COMMITTEE SCOPE MANUAL |
JM18U | Oct 2023 |
The JEDEC Board of Directors is responsible for establishing appropriate committees to conduct its standardization activities. This publication identifies the service and product committees established by the Board of Directors and defines their scopes. Committee(s): JC-COUN Free download. Registration or login required. |
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JEDEC COMMITTEE SPECIFIC ADDITIONAL POLICIES |
JM12B | Jun 2022 |
In some cases, JEDEC Committees have established additional policies and guidelines to facilitate the operation of a particular committee. Additional policies and guidelines are set forth here as an addendum to JM21 to facilitate the operation of particular committees. These policies are in addition to the requirements set forth in JM21 and in no case shall these additions contradict or supersede the requirements in JM21. Committee(s): JC-JEDC Free download. Registration or login required. |
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JEDEC GUIDELINE FOR THE CHARACTERIZATION OF HYBRID POLYMERIC MATERIALS - SUPERSEDED BY JESD72, June 2001Status: Rescinded |
JEP105 | Apr 1983 |
Committee(s): JC-13.5 Free download. Registration or login required. |
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JEDEC Legal Guidelines |
JM5.01 | Mar 2023 |
Terminology update. This document sets forth the best judgment of the standards of conduct and legal restraints that must be observed to protect against violations of the law. Free download. Registration or login required. |
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JEDEC Manual of Organization and Procedure |
JM21V | Nov 2023 |
This Manual sets forth the mission and requirements of JEDEC as an independent incorporated Association governed by a Board of Directors.
Committee(s): JC-BOD Free download. Registration or login required. |
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JEDEC Module Sideband Bus (SidebandBus) |
JESD403-1C.01 | Aug 2024 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Committee(s): JC-45 Free download. Registration or login required. |