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This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets.

Committee(s): JC-70.2

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This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results.

Committee(s): JC-70, JC-70.2

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This publication is intended for power GaAs FET applications requiring high reliability. An accurate measurement of thermal resistance is extremely important to provide the user with knowledge of the FETs operating temperature so that more accurate life estimates can be made. FET failure mechanisms and failure rates have, in general, an exponential dependence on temperature (which is why temperature-accelerated testing is successful). Because of the exponential relationship of failure rate with temperature, the thermal resistance should be referenced to the hottest part of the FET.

Committee(s): JC-14.7

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Committee(s): JC-14.4

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Committee(s): JC-22.2

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates. Also available for designer ease of use is HBM Ballout Spreadsheet (Note this version is the latest version for use with JESD235D). Committee item 1797.99L.

Committee(s): JC-42.3C

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The HBM4 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM4 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR).

The JESD271-4 HBM4 Bump Matrix Spreadsheet will be available in early May.

Patents(): There are several patent notifications claims in the JEDEC patent letter spreadsheet file for HBM. I do not know if any of these are going to be asserted against this HBM4 specification but this list is included in the BoD ballot content for reference.

Committee(s): JC-42, JC-42.2

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Release No. 17. Item 1755

Committee(s): JC-42, JC-42.2

JESD21-C Solid State Memory Documents Main Page

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The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices.  The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any).

Committee(s): JC-14.1

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