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Title	Document #	Date
FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES Status: Rescinded, November 2004	JESD34	Mar 1993
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD	JESD205	Mar 2007
This standard defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-45, JC-45.4 Free download. Registration or login required.
FBDIMM: ARCHITECTURE AND PROTOCOL	JESD206.01	Feb 2023
Terminology update. This standard includes four chapters of the FBD Channel Specification (cover) Channel Overview (Chapter 2), Initialization (Chapter 3), Channel Protocol (Chapter 4), and Reliability, Availability, and Serviceability (RAS) (Chapter 5). Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS Status: Rescinded February 2020	JESD22-C101F	Oct 2013
The material in this test method has been superseded by JS-002-2018, published January 2019, which in turn has been superseded by JS-002-2022, published January 2023. Committee(s): JC-14, JC-14.1
FILE NAMING CONVENTION:	JM19A	Sep 2017
Documents are frequently issued by the JEDEC Staff, the JEDEC Board of Directors (BoD), and the JEDEC Committees. It would be highly beneficial for all to use a uniform file-naming convention that would identify these documents by type, source, item or ballot number, date, and format of each file issued. The BoD Software Task Group has developed the file-designation system described below, in response to this need. It is based on an 8.3 file-name format, i.e., eight characters plus an extension of no more than three letters. Committee(s): JC-COUN Free download. Registration or login required.
FLIP CHIP TENSILE PULL	JESD22-B109C	Mar 2021
The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. Committee(s): JC-14.1 Free download. Registration or login required.
For Shunichi Saito only	TENTSTDSAITO
Editable file for JESD 209 -4 Graphics Free download. Registration or login required.
FORWARD TURN-ON TIME MEASUREMENT ON SEMI-DIODES - INCORPORATED INTO EIA-282-A. Status: Rescinded	JEP87	Jan 1992
Committee(s): JC-22.2
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)	JEP001-1A	Sep 2018
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)	JEP001-2A	Sep 2018
This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites)	JEP001-3B	Sep 2024
The publication provides methodologies for measurements to qualify a new semiconductor wafer process. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
Four Byte Modules and Cards Table of Contents	MODULE4.4.TOC	Jun 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Fully Buffered DIMM Design for Test, Design for Validation (DFx)	JESD82-28A.01	Mar 2023
Terminology update. This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40, JC-40.5 Free download. Registration or login required.
Gate Dielectric Breakdown	JESD263	Mar 2024
This document describes procedures developed for estimating the overall integrity of gate dielectrics. JESD263 supersedes these other 4 standards: JESD35A, JESD35-1 ADDENDUM, JESD35-2 and JESD92. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
GDDR2 Specific SGRAM Functions	SDRAM3.11.5.6	May 2005
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR3 Specific SGRAM Functions	SDRAM3.11.5.7	May 2005
Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR5 MEASUREMENT PROCEDURES	JEP171	Aug 2014
This publication is to inform all industry participants of a unified procedure to enable consistent measurement across the industry. This document contains the measurement procedures for testing GDDR5. Committee(s): JC-42.3 Free download. Registration or login required.
GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES	JESD31F	Aug 2021
This standard identifies the general requirements for Distributors that supply Commercial and Military products. This standard applies to all discrete semiconductors, integrated circuits and Hybrids, whether packaged or in wafer/die form, manufactured by all Manufacturers. The requirements defined within this document are only applicable to products for which ownership remains with the Distributor or Manufacturer. Committee(s): JC-13, JC-14.4 Free download. Registration or login required.

Standards & Documents Search

FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD

FBDIMM: ARCHITECTURE AND PROTOCOL

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS

FILE NAMING CONVENTION:

FLIP CHIP TENSILE PULL

For Shunichi Saito only

FORWARD TURN-ON TIME MEASUREMENT ON SEMI-DIODES - INCORPORATED INTO EIA-282-A.

FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)

FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites)

Four Byte Modules and Cards Table of Contents

Fully Buffered DIMM Design for Test, Design for Validation (DFx)

Gate Dielectric Breakdown

GDDR2 Specific SGRAM Functions

GDDR3 Specific SGRAM Functions

GDDR5 MEASUREMENT PROCEDURES

GENERAL REQUIREMENTS FOR DISTRIBUTORS OF COMMERCIAL AND MILITARY SEMICONDUCTOR DEVICES

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