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Title	Document #	Date
LOW TEMPERATURE STORAGE LIFE Status: Reaffirmed May 2021	JESD22-A119A	Oct 2015
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any). Committee(s): JC-14.1 Free download. Registration or login required.
APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY Status: Reaffirmed January 2021	JESD94B	Oct 2015
The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments. Committee(s): JC-14.3 Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 3 Release Number: 25	SPD4.1.2.L-3	Sep 2015
This annex describes the serial presence detect (SPD) values for all DDR4 modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in section 1.1 with the exception of bytes 128~255 which are documented in separate annexes, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2220.01F. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)	JESD209-3C	Aug 2015
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 25	MODULE4.20.27	Aug 2015
Item 2204.07 This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE Status: Reaffirmed January 2021	JESD22-A102E	Jul 2015
This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test that employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive. Committee(s): JC-14.1 Free download. Registration or login required.
DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION Status: Reaffirmed September 2020	JEP172A	Jul 2015
Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry. Committee(s): JC-14.3 Free download. Registration or login required.
Performance Standard - DDR4 288 Pin U/R/LR DIMM Connector Performance Standard	PS-002A	Jul 2015
This standard defines the form, fit and function of DDR4 connectors for U/R/LR modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.40 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the DDR4 connectors in client and server platforms. Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY	JEP159A	Jul 2015
This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
300 mV INTERFACE	JESD8-28	Jun 2015
This standard is to define and interface with a CMOS rail to rail signal that uses a 300 mV signal swing. This specification defines the maximum signaling rate, the signal levels, overshoot and undershoot limits, and the maximum input capacitance. This interface is useful in short distance applications, typically of less than 5 mm. Committee(s): JC-16 Free download. Registration or login required.
Annex G, R/C G, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification Release Number: 25	MODULE4.20.28.G	Jun 2015
Item 2241.06B This specification defines the electrical and mechanical requirements for Raw Card G, 288-pin, 1.2 Volt (VDD), Registered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM RDIMMs). These DDR4 Registered DIMMs (RDIMMs) are intended for use as main memory when installed in PCs. Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM	MO-309F	Mar 2015
Item No. 11.14-176 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - mSATA SSD Assembly. DIM.	MO-300C	Mar 2015
Item 11.14-175 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR4 MiniDIMM SMT 288 pin socket outline 0.50 mm pitch	SO-021A	Feb 2015
Item No. 11.14-174 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual Pitch Number Ball Grid Array Family, Square, 0.80 mm Major, 0.65 mm Minor Pitch. (T,V)F-SBGA	MO-315A	Feb 2015
Item No. 11-903 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Surface Mount Power Package with fused leads. H-PSOF	MO-299B	Jan 2015
Item 11.11-902 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Small Outline, Wide Body SOIC, 7.5 Body Width, 0.65 Pitch. R-PDSO.	MO-286B	Jan 2015
Item 11.10-450 Committee(s): JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
Dual Inline Memory Modules (DIMMs) Table of Contents	MODULE4.20.TOC	Dec 2014
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE	J-STD-048	Nov 2014
This document supersedes JESD48. This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. The goal of this notification standard is to better enable customers to manage and mitigate the disruption caused by the discontinuation of a product and ensure continuity of supply. This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition ongoing requirements to alternate products. Committee(s): JC-14.4 Free download. Registration or login required.
Standard Practices and Procedures - Registered and Standard Outlines	SPP-013A	Oct 2014
Item 11.2-886(E). This document has been editorially updated to provide template examples. Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

LOW TEMPERATURE STORAGE LIFE

APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGY

SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 3

LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)

288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification

ACCELERATED MOISTURE RESISTANCE - UNBIASED AUTOCLAVE

DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATION

Performance Standard - DDR4 288 Pin U/R/LR DIMM Connector Performance Standard

PROCEDURE FOR THE EVALUATION OF LOW-k/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY

300 mV INTERFACE

Annex G, R/C G, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Registered DIMM Design Specification

Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM

Registration - mSATA SSD Assembly. DIM.

Registration - DDR4 MiniDIMM SMT 288 pin socket outline 0.50 mm pitch

Registration - Dual Pitch Number Ball Grid Array Family, Square, 0.80 mm Major, 0.65 mm Minor Pitch. (T,V)F-SBGA

Registration - Surface Mount Power Package with fused leads. H-PSOF

Registration - Plastic Small Outline, Wide Body SOIC, 7.5 Body Width, 0.65 Pitch. R-PDSO.

Dual Inline Memory Modules (DIMMs) Table of Contents

JOINT JEDEC/IPC/ECIA STANDARD - NOTIFICATION STANDARD FOR PRODUCT DISCONTINUANCE

Standard Practices and Procedures - Registered and Standard Outlines

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