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Title	Document #	Date
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification Status: RescindedThis document is published as JESD248Release Number: 26	MODULE4.20.29	Oct 2016
See JESD248 Committee(s): JC-45.6 JESD21-C Solid State Memory Documents Main Page
VIBRATION, VARIABLE FREQUENCY	JESD22-B103B.01	Sep 2016
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). Committee(s): JC-14.1 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
UNDERSTANDING ELECTRICAL OVERSTRESS - EOS Status: Reaffirmed May 2022	JEP174	Sep 2016
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required.
Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).	DG-4.20F	Sep 2016
Item 11.2-820(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 9 Lead Surface Mount Power Package, 1.2 mm Pitch. H-PSOF	MO-327A	Sep 2016
Item No. 11-925 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)	DG-4.24B	Aug 2016
Item 11.2-850(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)	DG-4.25B	Aug 2016
This Design Requirement defines the symbols, definitions, algorithms, and specified dimensions and tolerances for Fine-pitch, LGA packages. The guidelines defined are based on hard metric dimensions and adhere to the geometric dimensioning and tolerancing principles defined in ASME Y14.5M-1994. Item 11.2-896(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, SQUARE, 0.40 mm Top, 0.40 mm Bottom Pitch. S-XBGA.	MO-302C	Aug 2016
Item No.11-930 Patents(): Amkor: 7,185,426; ASAT: 7,372,151; Texas Instruments: 7,675,152, 7,944034; Micron: 7,671,459 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.50 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-324A	Aug 2016
Item No. 11-926 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.65 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-325A	Aug 2016
Item No. 11-927 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.80 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-326A	Aug 2016
Item No. 11-928 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 12 Pin UFS Socket Outline, 0.91 mm Pitch. SKT	SO-022A	Aug 2016
Item No. 14-182 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS	J-STD-046	Jul 2016
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required.
SOLDER BALL PULL Status: Reaffirmed September 2021	JESD22-B115A.01	Jul 2016
This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Registration - 288 PIN DDR4 MINI DIMM, 0.50 MM PITCH	MO-314A.02	Jul 2016
Item 14-183, Minor Editorial Revision Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DDR4 260 Pin SODIMM Connector Performance Standard	PS-003A.01	Jul 2016
This standard defines the form, fit and function of SODIMM DDR4 connectors for modules supporting channels with transfer rates as high as 3.2 GT/S. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide Performance Standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR4 connectors in client and server platforms. Item 11.14-179E Patents(): FOXCONN US PATENT NO.: 5,882,211; 6,126,472; 6,113,398 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
MULTI-WIRE MULTI-LEVEL I/O STANDARD	JESD247	Jun 2016
This standard defines the DC and AC operating conditions, I/O impedances, termination characteristics, and compliance test methods of I/O drivers and receivers used in multi-wire, multi-level signaling interfaces. The multi-wire interfaces defined by this specification all utilize quaternary signal levels. Item 153.00 Patents(): Kandou Committee(s): JC-16 Free download. Registration or login required.
Annex B, Raw Card B, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SO-DIMM Design Specification Release Number: 26	MODULE4.20.25.B	Jun 2016
This annex defines the electrical and mechanical requirements for Raw Card B, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SO-DIMMs). These DDR4 SO-DIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Item no. 2228.17A Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex C, Raw Card C, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30	MODULE4.20.26.C	Jun 2016
This annex defines the electrical and mechanical requirements for Raw Card C, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Item 2231.37 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules