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Title	Document #	Date
LEAD INTEGRITY Status: Reaffirmed - May 2023	JESD22-B105E	Feb 2017
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Standard - Ball Grid Array Family, Square, 1.27 mm, and 1.50 mm Pitch. S-PBGA/PBGA.	MS-034G	Jan 2017
Item No. 11.11-933 (S) Item No. 11.11-723(S), Elevated MO-151 to Standard and included and increased Ax dimensions to allow for thicker packages. Patents(): National Semiconductor: 4688152; 4778641; 4868349. Citizen Watch Company: 4822550; 4935581. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Ball Grid Array Family, Square, 1.00 mm Pitch. PBGA	MO-318B	Jan 2017
Item 11.11-934 Outline Cross Reference: Design Registration 4.14 (DR4.14) Patents(): May apply: National – 4688152, 4778641, 4868349. Citizen – 4822550, 4935581 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)	JESD8-29	Dec 2016
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24. Committee(s): JC-16 Free download. Registration or login required.
RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES Status: Reaffirmed February 2023	JESD22-B106E	Nov 2016
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s): JC-14.1 Free download. Registration or login required.
EMBEDDED MULTIMEDIACARD (e•MMC) SECURITY EXTENSION Item 65.02	JESD227	Nov 2016
This document provides a comprehensive definition of the e•MMC Security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. Committee(s): JC-64.1 Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSION Item 112.99	JESD225	Nov 2016
This document provides a comprehensive definition of the UFS security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. Committee(s): JC-64.1 Free download. Registration or login required.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification Status: RescindedThis document is published as JESD248Release Number: 26	MODULE4.20.29	Oct 2016
See JESD248 Committee(s): JC-45.6 JESD21-C Solid State Memory Documents Main Page
VIBRATION, VARIABLE FREQUENCY	JESD22-B103B.01	Sep 2016
The Vibration, Variable Frequency Test Method is intended to determine the ability of component(s) to withstand moderate to severe vibration as a result of motion produced by transportation or filed operation of electrical equipment. This is a destructive test that is intended for component qualification. This is a minor editorial change to JESD22-B103B, June 2002 (Reaffirmed September 2010). Committee(s): JC-14.1 Free download. Registration or login required.
FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES	JEP122H	Sep 2016
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
UNDERSTANDING ELECTRICAL OVERSTRESS - EOS Status: Reaffirmed May 2022	JEP174	Sep 2016
This purpose of this white paper will be to introduce a new perspective about EOS to the electronics industry. As failures exhibiting EOS damage are commonly experienced in the industry, and these severe overstress events are a factor in the damage of many products, the intent of the white paper is to clarify what EOS really is and how it can be mitigated once it is properly comprehended. Committee(s): JC-14.3 Free download. Registration or login required.
Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).	DG-4.20F	Sep 2016
Item 11.2-820(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 9 Lead Surface Mount Power Package, 1.2 mm Pitch. H-PSOF	MO-327A	Sep 2016
Item No. 11-925 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)	DG-4.24B	Aug 2016
Item 11.2-850(S) Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)	DG-4.25B	Aug 2016
This Design Requirement defines the symbols, definitions, algorithms, and specified dimensions and tolerances for Fine-pitch, LGA packages. The guidelines defined are based on hard metric dimensions and adhere to the geometric dimensioning and tolerancing principles defined in ASME Y14.5M-1994. Item 11.2-896(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, SQUARE, 0.40 mm Top, 0.40 mm Bottom Pitch. S-XBGA.	MO-302C	Aug 2016
Item No.11-930 Patents(): Amkor: 7,185,426; ASAT: 7,372,151; Texas Instruments: 7,675,152, 7,944034; Micron: 7,671,459 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.50 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-324A	Aug 2016
Item No. 11-926 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.65 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-325A	Aug 2016
Item No. 11-927 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Lower PoP Ball Grid Array Family, Square, 0.80 mm Top, 0.50 mm Bottom Pitch. S-XBGA	MO-326A	Aug 2016
Item No. 11-928 Patents(): Micron: 6,048,758. Tessera: 5,950,304; 6,133,627 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 12 Pin UFS Socket Outline, 0.91 mm Pitch. SKT	SO-022A	Aug 2016
Item No. 14-182 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

LEAD INTEGRITY

Standard - Ball Grid Array Family, Square, 1.27 mm, and 1.50 mm Pitch. S-PBGA/PBGA.

Registration - Ball Grid Array Family, Square, 1.00 mm Pitch. PBGA

0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)

RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICES

EMBEDDED MULTIMEDIACARD (e•MMC) SECURITY EXTENSION

UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSION

288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/ PC4-3200 DDR4 SDRAM Non-Volatile NAND-Flash DIMM Design Specification

VIBRATION, VARIABLE FREQUENCY

FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES

UNDERSTANDING ELECTRICAL OVERSTRESS - EOS

Design Requirements - Small Scale Plastic Quad and Dual Inline, Square and Rectangular, No-Lead Packages (With Optional Thermal Enhancements). Small Scale (QFN/SON).

Registration - 9 Lead Surface Mount Power Package, 1.2 mm Pitch. H-PSOF

Design Requirements - Scalable Quad Flat No-lead Packages, Square and Rectangular (Scalable QFN)

Design Requirements - Fine-Pitch, Land Grid Array Package, Square and Rectangular (FLGA, FRLGA)

Registration - Lower PoP Ball Grid Array Family, SQUARE, 0.40 mm Top, 0.40 mm Bottom Pitch. S-XBGA.

Registration - Lower PoP Ball Grid Array Family, Square, 0.50 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - Lower PoP Ball Grid Array Family, Square, 0.65 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - Lower PoP Ball Grid Array Family, Square, 0.80 mm Top, 0.50 mm Bottom Pitch. S-XBGA

Registration - 12 Pin UFS Socket Outline, 0.91 mm Pitch. SKT

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