Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
STANDARD LOGNORMAL ANALYSIS OF UNCENSORED DATA, AND OF SINGLY RIGHT -CENSORED DATA UTILIZING THE PERSSON AND ROOTZEN METHOD: |
JESD37A | Aug 2017 |
This standard details techniques for estimating the values of a two parameter lognormal distribution from complete lifetime data (all samples in an experiment have failed) or singly right-censored lifetime data (the experiment have failed) or singly right-censored lifetime data gathered from rapid stress test; however, not all types of failure data can be analyzed with these techniques. Committee(s): JC-14.2 Free download. Registration or login required. |
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DDR4 PROTOCOL CHECKS |
JEP175 | Jul 2017 |
The intended use of this document is for the validation and debug of DDR4 based designs. This document contains protocol checks, sometimes referred to as memory access rules or protocol violations. This document contains a list of checks that can be used during the verification or debug stages of development to check that accesses to a DDR4 DRAM adhere to JESD79-4B. These checks are derived from JESD79-4B. Item 31509. Committee(s): JC-40.5 Free download. Registration or login required. |
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UNIVERSAL FLASH STORAGE (UFS) TEST |
JESD224A | Jul 2017 |
JESD224A is valid only for UFS 2.1 and should not be referenced for other versions of the UFS standard. The primary objective of this test standard is to specify the test cases for UFS device protocol conformance testing. This test standard provides test cases for checking the functions defined in the following target standard: JESD220. Universal Flash Storage (UFS) Standard version 1.1A. MIPI M-PHY and MIPI UniPro test cases are not in the scope of this document. Item 400.36 Committee(s): JC-64.5 Free download. Registration or login required. |
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Annex H, Raw Card H, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design SpecificationRelease Number: 27 |
MODULE4.20.25.H | Jun 2017 |
Item 2228.28. Editorial This specification defines the electrical and mechanical requirements for Raw Card H, 260-pin, 1.2 Volt (VDD), Small Outline, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM SODIMMs). These DDR4 SODIMMs are intended for use as main memory when installed in PCs, laptops, and other systems. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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INSPECTION CRITERIA FOR MICROELECTRONIC PACKAGES AND COVERSStatus: Reaffirmed May 2023 |
JESD9C | May 2017 |
The purpose of this JEDEC standard is to verify the workmanship and requirements of microelectronic packages and covers (lids) intended for use in fabricating hybrid microelectronic circuits/microcircuits (hereafter referred to as “microcircuits”). It is applicable for use by the package manufacturer (i.e., package components), and the microcircuit manufacturer (i.e., from incoming inspection of package components through final inspection of the completed microcircuit). This standard also encompasses and replaces JESD27, Ceramic Package Specification for Microelectronic Packages. It is meant to be used in conjunction, and to not contradict, with MIL-STD-883, Test Method 2009: External Visual. Free download. Registration or login required. |
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WIRE BOND SHEAR TEST |
JESD22-B116B | May 2017 |
This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance. Free download. Registration or login required. |
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STANDARD TEST METHOD UTILIZING X-RAY FLUORESCENCE (XRF) FOR ANALYZING COMPONENT FINISHES AND SOLDER ALLOYS TO DETERMINE TIN (Sn) - LEAD (Pb) CONTENTReaffirmed June 2023 |
JESD213A | Apr 2017 |
This document is intended to be used by Original Component Manufacturers who deliver electronic components and Original Equipment Manufacturers who are the platform system integrators. It is intended to be applied prior to delivery by the OCMs and may be used by OEM system engineers and procuring activities as well as U.S Government Department of Defense system engineers, procuring activities and repair centers. This Standard establishes the instrumentation, techniques, criteria, and methods to be utilized to quantify the amount of Lead (Pb) in Tin-Lead (Sn/Pb) alloys and electroplated finishes containing at least 3 weight percent (wt%) Lead (Pb) using X-Ray Fluorescence (XRF) equipment. Reaffirmed June 2023
Committee(s): JC-13 Free download. Registration or login required. |
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FAILURE-MECHANISM-DRIVEN RELIABILITY MONITORINGStatus: Reaffirmed June 2011, May 2022 |
JESD659C | Apr 2017 |
This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999. Free download. Registration or login required. |
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Registration - Upper PoP Ball Grid Array Family, Square, 0.50 mm Pitch. PBGA |
MO-321A.01 | Mar 2017 |
Item No. 11-941(E) Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Upper PoP Ball Grid Array Family, Square, 0.65 mm Pitch. PBGA |
MO-322A.01 | Mar 2017 |
Item No. 11-941(E) Committee(s): JC-11.11 Free download. Registration or login required. |
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Registration - Upper PoP Ball Grid Array Family, Square, 0.40 mm Pitch. PBGA |
MO-323A.01 | Mar 2017 |
Item No. 11-941(E) Committee(s): JC-11.11 Free download. Registration or login required. |
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AVALANCHE BREAKDOWN DIODE (ABD) TRANSIENT VOLTAGE SUPPRESSORS |
JESD210A | Mar 2017 |
This standard is applicable to avalanche breakdown diodes when used as a surge protector or transient voltage suppressor (TVS). It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. This standard may be applied to other surge-protection components with similar characteristics as the ABD. Committee(s): JC-22.2, JC-22.5 Free download. Registration or login required. |
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Registration - Flange Mounted Family, Surface Mount, Peripheral Terminals. R-PSFM-G. |
TO-252F | Feb 2017 |
Item 11.10-456 Committee(s): JC-11.10 Free download. Registration or login required. |
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LEAD INTEGRITYStatus: Reaffirmed - May 2023 |
JESD22-B105E | Feb 2017 |
This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user. Free download. Registration or login required. |
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Standard - Ball Grid Array Family, Square, 1.27 mm, and 1.50 mm Pitch. S-PBGA/PBGA. |
MS-034G | Jan 2017 |
Item No. 11.11-933 (S) Patents(): National Semiconductor: 4688152; 4778641; 4868349. Citizen Watch Company: 4822550; 4935581. Free download. Registration or login required. |
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Registration - Ball Grid Array Family, Square, 1.00 mm Pitch. PBGA |
MO-318B | Jan 2017 |
Item 11.11-934 Outline Cross Reference: Design Registration 4.14 (DR4.14) Patents(): May apply: National – 4688152, 4778641, 4868349. Citizen – 4822550, 4935581 Free download. Registration or login required. |
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0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06) |
JESD8-29 | Dec 2016 |
This standard defines power supply voltage range, dc interface, switching parameter and overshoot/undershoot for high speed low voltage swing terminated NMOS driver family digital circuits with 0.6V supply. The specifications in this standard represent a minimum set of interface specifications for low voltage terminated circuits. Item 180.24. Committee(s): JC-16 Free download. Registration or login required. |
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RESISTANCE TO SOLDER SHOCK FOR THROUGH-HOLE MOUNTED DEVICESStatus: Reaffirmed February 2023 |
JESD22-B106E | Nov 2016 |
This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board. Committee(s): JC-14.1 Free download. Registration or login required. |
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EMBEDDED MULTIMEDIACARD (e•MMC) SECURITY EXTENSIONItem 65.02 |
JESD227 | Nov 2016 |
This document provides a comprehensive definition of the e•MMC Security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. Committee(s): JC-64.1 Free download. Registration or login required. |
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UNIVERSAL FLASH STORAGE (UFS) SECURITY EXTENSIONItem 112.99 |
JESD225 | Nov 2016 |
This document provides a comprehensive definition of the UFS security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead. Committee(s): JC-64.1 Free download. Registration or login required. |
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