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Title	Document #	Date
SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD	JESD218B.03	Aug 2024
Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser. Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32 Committee(s): JC-64.8 Available for purchase: $76.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Guidelines for Reverse Recovery Time and Charge Measurement of SiC MOSFET Version 1.0	JEP201	Aug 2024
This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
PLASTIC DUAL FLATPACK, SURFACE TERMINAL, 1.27 MM PITCH RECTANGULAR FAMILY PACKAGE	MO-364A	Aug 2024
Designator:PDFN-N[#]_I1p27... Item #: 11-1063 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC Module Sideband Bus (SidebandBus)	JESD403-1C.01	Aug 2024
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Committee(s): JC-45 Free download. Registration or login required.
Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements	JEP30-T100B	Aug 2024
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-15 Free download. Registration or login required.
LPDDR5 CAMM2 Connector Performance Standard	PS-007A	Jul 2024
LPDDR5 CAMM2 Connector Performance Standard Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.50 MM PITCH RECTANGULAR FAMILY PACKAGE	MO-363A	Jul 2024
Designator: PBGA-B#[#]_I0p5... Item #: 11-1066 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE	MO-359B	Jul 2024
Designator: H-PDSO-G12_12p0-12p0x9p4Z2p8 Item No: 11-1049 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Style Manual for Standards and Other Publications of JEDEC	JM7A	Jul 2024
This manual establishes requirements for the preparation of standards and certain other publications of the JEDEC Solid State Technology Association. Committee(s): JC-10 Free download. Registration or login required.
DDR5 SDRAM Release Number: Version 1.31	JESD79-5C.01	Jul 2024
Version 1.31 This standard defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Committee(s): JC-42, JC-42.3 Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access.
PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)	TO-282A	Jun 2024
Package Designator: PMDF-T5_I2p54... Item # 11-1058 Patents(): Owners: - Otremba, Ralf - Kasztelan, Christian - Fuergut, Edward - Lee, Teck Sim - Wang, Lee Shuang - Kuek, Hsieh Ting - Murugan, Sanjay Kumar Company: - Infineon Technologies AG, 85579 Neubiberg, DE Patent Number (Germany): - DE 102015109073 B4 Title: - Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
MCP and Discrete e•MMC, e•2MMC, and UFS Release Number: 33	MCP3.12.1-1	Jun 2024
Item 142.12 This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1	JEP200	Jun 2024
This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices. Committee(s): JC-70, JC-70.1, JC-70.2 Free download. Registration or login required.
DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY	MO-358B	Jun 2024
Designator: XBNA-N#_I1p0_... Item No: 14-229 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC® Memory Module Label – for Compute Express Link® (CXL®) Release Number: 1.1	JESD405-1B	Jun 2024
This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. Committee(s): JC-45 Free download. Registration or login required.
Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)	JEP170A	Jun 2024
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
Information Requirements for the Qualification of Solid State Devices	JESD69D	Jun 2024
This standard defines the requirements for the device qualification package, which the supplier provides to the customer. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Board Level Drop Test Method of Components for Handheld Electronic Products	JESD22-B111A.01	Jun 2024
This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD04)	JESD82-514.01	Jun 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
Low Power Double Data Rate 4 (LPDDR4)	JESD209-4E	Jun 2024
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Committee(s): JC-42, JC-42.6 Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access.

Standards & Documents Search

SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD

Guidelines for Reverse Recovery Time and Charge Measurement of SiC MOSFET Version 1.0

PLASTIC DUAL FLATPACK, SURFACE TERMINAL, 1.27 MM PITCH RECTANGULAR FAMILY PACKAGE

JEDEC Module Sideband Bus (SidebandBus)

Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

LPDDR5 CAMM2 Connector Performance Standard

PLASTIC BOTTOM GRID, ARRAY BALL, 0.60 MM X 0.50 MM PITCH RECTANGULAR FAMILY PACKAGE

PLASTIC DUAL SMALL OUTLINE, GULL WING, 2.00 MM PITCH, RECTANGULAR PACKAGE

Style Manual for Standards and Other Publications of JEDEC

DDR5 SDRAM

PLASTIC FLANGE MOUNT, THROUGH-HOLE, 2.54 MM PITCH RECT PACKAGE (TRANSISTOR)

MCP and Discrete e•MMC, e•2MMC, and UFS

Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1

DDR5 CAMM2, 1.00 MM X 1.38 MM PITCH, MICROELECTRONIC ASSEMBLY

JEDEC® Memory Module Label – for Compute Express Link® (CXL®)

Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)

Information Requirements for the Qualification of Solid State Devices

Board Level Drop Test Method of Components for Handheld Electronic Products

DDR5 Registering Clock Driver Definition (DDR5RCD04)

Low Power Double Data Rate 4 (LPDDR4)

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