Standards & Documents Search

Displaying 41 - 60 of 1418 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-25.01	Jan 2023
Terminology update.This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS	JESD82-26.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD Release Number: C.01 - Terminology update	JESD212C.01	Jan 2023
Terminology update. This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required.
DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-23.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. Committee(s): JC-40 Free download. Registration or login required.
Joint ESDA/JEDEC - CDM Technical User Guide	JTR002-01-22	Jan 2023
This report only covers the procedures and requirements specified in ANSI/ESDA/JEDEC JS-002. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DDR5 Serial Presence Detect (SPD) Contents Terminology update Release Number: Version 1.1	JESD400-5A.01	Jan 2023
This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be used by the system's BIOS in order to properly initialize and optimize the system memory channels. Committee(s): JC-45 Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESDJESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
HIGH BANDWIDTH MEMORY (HBM3) DRAM	JESD238A	Jan 2023
The HBM3 DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM3 DRAM uses a wide-interface architecture to achieve high-speed, low power operation. Each channel interface maintains a 64 bit data bus operating at double data rate (DDR). Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42, JC-42.2 Free download. Registration or login required.
Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs	JEP183A	Jan 2023
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET	JEP192	Jan 2023
This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS	JEP163A	Jan 2023
This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL	JS-002-2022	Jan 2023
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
IC LATCH-UP TEST	JESD78F.01	Dec 2022
This standard covers the I-test and Vsupply overvoltage latch-up testing of integrated circuits. The purpose of this standard is to establish a method for determining IC latch-up characteristics and to define latch-up detection criteria. Latch-up characteristics are extremely important in determining product reliability and minimizing No Trouble Found (NTF) and Electrical Overstress (EOS) failures due to latch-up. This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies. This standard has been adopted by the Defense Logistics Agency (DLA) as project 5962-1880. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JEDEC Manual of Organization and Procedure	JM21U	Dec 2022
The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process. NOTE The .pdf file has been updated as of 1/12/2023, there was an side comment in 7.2 that was included at time of conversion and has been removed. Committee(s): JC-BOD Free download. Registration or login required.
JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)	J-STD-020F	Dec 2022
The purpose of this standard is to identify the classification level of non-hermetic SMDs that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow attachment and/or repair operations. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices	J-STD-035A	Dec 2022
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A.01	Dec 2022
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS	JESD47L	Dec 2022
This standard describes a baseline set of acceptance tests for use in qualifying electronic components as new products, a product family, or as products in a process which is being changed. Committee(s): JC-14, JC-14.3 Available for purchase: $87.38 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.

Standards & Documents Search

DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

DEFINITION OF the SSTUA32S869 AND SSTUA32D869 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

Joint ESDA/JEDEC - CDM Technical User Guide

DDR5 Serial Presence Detect (SPD) Contents

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

HIGH BANDWIDTH MEMORY (HBM3) DRAM

Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs

Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS

Survey On Latch-Up Testing Practices and Recommendations for Improvements

ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL

THERMAL SHOCK

IC LATCH-UP TEST

JEDEC Manual of Organization and Procedure

JOINT IPC/JEDEC Standard Moisture/Reflow Sensitivity Classification for Non-hermetic Surface Mount Devices (SMDs)

JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices

PROCESS CHARACTERIZATION GUIDELINE

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: