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Title	Document #	Date
Dynamic Random Access Memory (DRAM) Table of Contents	DRAM3.9.TOC	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Stacked TSOPII Package (2 and 4 High). Item 11.11-429. April 2003	MO-201-A	Oct 1997
This outline has been inactivated, please see attachment. The file can be located by going to the JEP95 Main Page, under Microelectronic Outlines, Archives. Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
72 Pin DRAM SIMM	MODULE4.4.2	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
80 Pin EEPROM SIMM	MODULE4.4.7	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex C, Fast Page and Extended Data Out RAM	SPD4.1.2.3	Jan 1998
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
NATIONAL ELECTRONIC PROCESS CERTIFICATION STANDARD; GOVERNMENT CONTRACTORS: Removed: August 25, 2003	EIA599-A	Jan 1998
Due to notification from the JC-14.4 subcommittee that the material contained in EIA599 has been replaced by the ISO 9000 series, the JEDEC Board of Directors, at its August 2003 meeting, approved to remove this standard from the JEDEC Free Download Area. Committee(s): JC-14.4
Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.	DG-4.16A	Feb 1998
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
SPD Annex F, Address Multiplexed ROM	SPD4.1.2.6	Jun 1998
Release No.8 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Plastic Chip Carrier (PLCC) Shipping/Handling Tubes. Item 11.5-501.	CO-033-A	Aug 1998
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS: Status: Reaffirmed January 2025	JEP134	Sep 1998
The purpose of this Guideline is to provide a vehicle for acquiring and transmitting the necessary information in a concise, organized, and consistent format. Included in the Guideline is a sample form that facilitates transferring the maximum amount of background data to the failure analyst in a readily interpretable format. Immediate availability of this key information assists that analyst in completing a timely and accurate failure analysis. Committee(s): JC-14.4 Free download. Registration or login required.
Standard - TSOP II, Thin Matrix Tray for Shipping and Handling of FBGA's. Item 11.5-519.	CS-005-B	Nov 1998
Committee(s): JC-11, JC-11.5 JEP95 Registrations Main Page Free download. Registration or login required.
EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS:	JESD51- 5	Feb 1999
This extension of the thermal standards provides a standard fixture for direct attach type packages such as deep-downset of thermally tabbed packages. This specification provides additional design detail for use in developing thermal test boards with application to these package types. This document is in addition to and not replacement for the design specifications in other standards. Committee(s): JC-15.1 Free download. Registration or login required.
HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:	JESD51- 7	Feb 1999
This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. The objective of the standard is to provide a high effective thermal conductivity mounting surface that can be compared equally against standard tests done in different laboratories with typical variations of less than or equal to 10%. Committee(s): JC-15.1 Free download. Registration or login required.
I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD:	JESD67	Feb 1999
This standard attempts to aid in the design of electronic systems comprised of components that operate at several different supply voltages. This document covers respectively configurable I/O voltage, receiver type and switchpoint, and driver impedance. Committee(s): JC-16 Free download. Registration or login required.
INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR):	JESD51- 6	Mar 1999
This standard specifies the environmental conditions for determining thermal performance of an integrated circuit device in a forced convection environment when mounted on a standard thermal test board. Committee(s): JC-15.1 Free download. Registration or login required.
168 Pin DRAM DIMM	MODULE4.5.1	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin DRAM SO-DIMM	MODULE4.5.5	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin SDRAM SO-DIMM	MODULE4.5.6	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin DDR SGRAM SO-DIMM	MODULE4.5.9	Mar 1999
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

Dynamic Random Access Memory (DRAM) Table of Contents

Registration - Stacked TSOPII Package (2 and 4 High). Item 11.11-429.

72 Pin DRAM SIMM

80 Pin EEPROM SIMM

100 Pin DRAM, SDRAM, and ROM DIMM

SPD Annex C, Fast Page and Extended Data Out RAM

NATIONAL ELECTRONIC PROCESS CERTIFICATION STANDARD; GOVERNMENT CONTRACTORS:

Design Requirements - Plastic Ultra-Thin Small outline No-Lead Package. R-PDSO-N/USON.

SPD Annex F, Address Multiplexed ROM

Registration - Plastic Chip Carrier (PLCC) Shipping/Handling Tubes. Item 11.5-501.

GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS:

Standard - TSOP II, Thin Matrix Tray for Shipping and Handling of FBGA's. Item 11.5-519.

EXTENSION OF THERMAL TEST BOARD STANDARDS FOR PACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS:

HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PACKAGES:

I/O DRIVERS AND RECEIVERS WITH CONFIGURABLE COMMUNICATION VOLTAGE, IMPEDANCE, AND RECEIVER THRESHOLD:

INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CONVECTION (MOVING AIR):

168 Pin DRAM DIMM

144 Pin DRAM SO-DIMM

144 Pin SDRAM SO-DIMM

144 Pin DDR SGRAM SO-DIMM

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