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Displaying 41 - 60 of 1419 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title Document # Datesort ascending

Temperature Cycling

 JESD22-A104F.01 Apr 2023

This standard applies to single-, dual- and triple-chamber temperature cycling in an air or other gaseous medium and covers component and solder interconnection testing.

Committee(s): JC-14.1

Free download. Registration or required.

Registration - Plastic Quad Flat Package, Gull Wing and J-Lead, 0.65 MM Pitch

 MO-355A Apr 2023

Designator: PQFP-E#_I0p65-R...
Item: 11.11-1028, Access STP File for MO-355A
Cross Reference: N/A

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or required.

Graphics Double Data (GDDR4) SGRAM Standard

Release Number: 16 		SDRAM3.11.5.8 R16.01 Mar 2023

Item 1600.41, Terminology Update  

This document defines the Graphics Double Data Rate 4 (GDDR4) Synchronous Graphics Random

Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or required.

Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

Release Number: 32 		MCP3.12.1 Mar 2023

Item 140.07B.

This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.

 

Committee(s): JC-64.2

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or required.

Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications

 JESD82-27.01 Mar 2023

Terminology update.  

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM.

Committee(s): JC-40

Free download. Registration or required.

Fully Buffered DIMM Design for Test, Design for Validation (DFx)

 JESD82-28A.01 Mar 2023

Terminology update.  

This FBDIMM DFx standard covers Design for Test, Design for Manufacturing, and Design for Validation (“DFx”) requirements and implementation guidelines for Fully Buffered DIMM technology.

Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents.

Committee(s): JC-40, JC-40.5

Free download. Registration or required.

RADIO FRONT END - BASEBAND DIGITAL PARALLEL (RBDP) INTERFACE

 JESD207.01 Mar 2023

Terminology update.  

This document establishes an interface standard for the data path and control plane interface functions for an RFIC component and/or a BBIC component.

Committee(s): JC-61

Free download. Registration or required.

GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD

 JESD232A.01 Mar 2023

Terminology update.  

This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package

Committee(s): JC-42.3, JC-42.3C

Free download. Registration or required.

SILICON RECTIFIER DIODES:

 JESD282B.02 Mar 2023

Terminology update.   

This legacy document is a comprehensive users’ guide for silicon rectifier diode applications.

Committee(s): JC-22.2

Free download. Registration or required.

DEFINITION OF THE SSTVN16859 2.5-2.6 V 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR PC1600, PC2100, PC2700 AND PC3200 DDR DIMM APPLICATIONS

 JESD82-13A.01 Mar 2023

Terminology update.   

Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL_2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications

Committee(s): JC-40

Free download. Registration or required.

JEDEC Legal Guidelines

 JM5.01 Mar 2023

Terminology update.  

This document sets forth the best judgment of the standards of conduct and legal restraints that must be observed to protect against violations of the law.

Free download. Registration or required.

COMPACT THERMAL MODEL OVERVIEW

 JESD15-1.01 Mar 2023

Terminology update.

This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents.

Committee(s): JC-15, JC-15.1

Free download. Registration or required.

RADIO FRONT END - BASEBAND (RF-BB) INTERFACE

 JESD96A.01 Mar 2023

Terminology update.  

This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

Committee(s): JC-61

Free download. Registration or required.

Compute Express Link (CXL™) Memory Module Base Standard

 JESD317 Mar 2023

This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules.

The purpose is to provide certain reference base targets for CXL™-attached memory modules to enable system design simplification, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-45

Free download. Registration or required.

Registration - Plastic Bottom Grid Array, 0.80 MM Pitch, Rectangular Family Package

 MO-210R Mar 2023

Designator: PBGA-B#[#]_I0p...

 

Item: 11.11-988, Access STP Files for MO-210R

Cross Reference: DG4.5

https://www.jedec.org/filebrowser/download/1625

Patents(): May apply: Micron: 6,048,753. Tessera: 5,950,304; and 6,133,627

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or required.

Registration - Plastic Bottom Grid Array Ball, 0.40 MM Pitch Rectangular Family Package

 MO-352A.01 Mar 2023

Designator: PBGA-B#[#}_I0p4...
Item: 11.11-1006E (Minor editorial Change), Access STP File for MO-352A.01
Cross Reference: N/A

Committee(s): JC-11.11

JEP95 Registrations Main Page

Free download. Registration or required.

Part Model SupplyChain Guidelines for Electronic-Device Packages – XML Requirements

 JEP30-S100 Mar 2023

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, supply chain, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the SupplyChain sub-section of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14.4

Free download. Registration or required.

Part Model Thermal Guidelines for Electronic-Device Packages – XML Requirements

 JEP30-T100A Mar 2023

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Thermal" subsection of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-15

Free download. Registration or required.

Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

 JEP30-A100A Mar 2023

This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts.  This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model.

For more information visit the main JEP30 webpage.

Committee(s): JC-11, JC-11.2, JC-14.4

Free download. Registration or required.

DDR5 Registering Clock Driver Definition (DDR5RCD03)

Release Number: 1.00 		JESD82-513 Feb 2023

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD03 Device ID is DID = 0x0053.

Committee(s): JC-40, JC-40.5

Free download. Registration or required.

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