Standards & Documents Search

Displaying 21 - 40 of 1459 documents. Show 5 | 10 | 20 | 40 | 60 results per page.

Title	Document #	Date
Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard	JESD326-4	Nov 2024
This standard defines the Low Power Double Data Rate interface for Non-Volatile Memory (LPDDR4XNVM) Standard. This standard describes features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit single channel LPDDR4X-NVM device. LPDDR4X-NVM density ranges from 128Mb through 32Gb. Committee(s): JC-42, JC-42.6 Free download. Registration or login required.
LPDDR5/5X Serial Presence Detect (SPD) Contents Release Number: 1.0	JESD406-5A	Nov 2024
This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding. Committee(s): JC-45 Free download. Registration or login required.
JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL	JS-001-2024	Oct 2024
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230G	Oct 2024
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
DDR5 262 Pin SODIMM Connector Performance Standard	PS-006B	Sep 2024
This standard defines the form, fit and function of SODIMM DDR5 connectors for modules supporting channels with transfer rates 6.4 GT/S and beyond. It contains mechanical, electrical and reliability requirements for a one-piece connector mated to a module with nominal thickness of 1.20 mm. The intent of this document is to provide performance standards to enable connector, system designers and manufacturers to build, qualify and use the SODIMM DDR5 connectors in client and server platforms. Item 14-226 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE	JEP106BK	Sep 2024
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
Graphics Double Data Rate 7 SGRAM Standard (GDDR7)	JESD239A	Sep 2024
This standard defines the Graphics Double Data Rate 7 (GDDR7) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. Committee(s): JC-42, JC-42.1 Free download. Registration or login required.
Wire Bond Pull Test Methods	JESD22-B120.01	Sep 2024
This test method provides a means for determining the strength and failure mode of a wire bonded to, and the corresponding interconnects on, a die or package bonding surface and may be performed on pre-encapsulation or post-encapsulation devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)	JESD319	Sep 2024
This standard defines the overall specifications, interface parameters, signaling protocols, and features for a CXL® Memory Controller ASIC. The standard includes pinout information, functional description, and configuration interface. This standard, along with other Referenced Specifications, should be treated as a whole for the purposes of defining overall functionality for CXL® Memory Controller (referred to as CMC). Committee(s): JC-40 Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, GULL WING, 0.95 MM PITCH, RECT PACKAGE (TRANSISTOR)	TO-236-I	Sep 2024
Item #: 11-1067 Package Designator: PDSO-G3(6)-i0p95.... Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)	JESD325	Sep 2024
This standard provides a reference specification for systems and device management capabilities found in CXL memory devices. It is intended to target, but may not be limited to, CXL memory FRUs that are based on PCIe Gen 5 and compliant to the CXL 2.0 Specification or later. Committee(s): JC-40, JC-45 Free download. Registration or login required.
DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS Release Number: Release 1.3	JESD400-5C	Sep 2024
This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. Committee(s): JC-45 Free download. Registration or login required.
Temperature Range and Measurement Standards for Components and Modules	JESD402-1B	Sep 2024
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Committee(s): JC-42 Free download. Registration or login required.
PLASTIC DUAL FLANGE MOUNT, 2.00 MM PITCH RECT PACKAGE (TRANSISTOR)	TO-283A	Sep 2024
Item #11-1060 Package Designator: PDFM-E5_I2p0.... Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites)	JEP001-3B	Sep 2024
The publication provides methodologies for measurements to qualify a new semiconductor wafer process. Committee(s): JC-14, JC-14.2 Free download. Registration or login required.
PLASTIC MULTI SMALL OUTLINE, 1.20 MM PITCH PACKAGE 1.14 MM PITCH, 15.40 MM BODY WIDTH, RECT FAMILY PACKAGE	MO-354B	Sep 2024
Item: 11-1065 Designator: PMSO-E#_I1p14-... Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
PLASTIC BOTTOM GRID ARRAY BALL, 0.80 MM PITCH, SQUARE FAMILY PACKAGE	MO-216H	Sep 2024
Designator: PBGA-B#[#]_I80... Item: 11-1064 Cross Reference: DR4.5 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements	JEP30-A100B	Aug 2024
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Assembly Process Classification” subsection of the Part Model. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14.4 Free download. Registration or login required.
Part Model Guidelines for Electronic-Device Packages – XML Requirements	JEP30E	Aug 2024
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It covers several sub-sections such as electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the parental structure, under which several sub-section listed above, can be contained and linked together within the Part Model parent structure. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2 Free download. Registration or login required.
PLASTIC DUAL SMALL OUTLINE, RECTANGULAR FAMILY PACKAGE	MO-153I	Aug 2024
Package Designator: PDSO-G#-I##.... Item# - JC11.11-1069 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

Low Power Double Data Rate Interface for Non-Volatile Memory (LPDDR4X-NVM) Standard

LPDDR5/5X Serial Presence Detect (SPD) Contents

JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - DEVICE LEVEL

NAND Flash Interface Interoperability

DDR5 262 Pin SODIMM Connector Performance Standard

STANDARD MANUFACTURERS IDENTIFICATION CODE

Graphics Double Data Rate 7 SGRAM Standard (GDDR7)

Wire Bond Pull Test Methods

JEDEC® Memory Controller Standard – for Compute Express Link® (CXL®)

PLASTIC DUAL SMALL OUTLINE, GULL WING, 0.95 MM PITCH, RECT PACKAGE (TRANSISTOR)

JEDEC® Memory Device Management Standard – for Compute Express Link® (CXL®)

DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTS

Temperature Range and Measurement Standards for Components and Modules

PLASTIC DUAL FLANGE MOUNT, 2.00 MM PITCH RECT PACKAGE (TRANSISTOR)

Foundry Process Qualification Guidelines – Technology Qualification Vehicle Testing (Wafer Fabrication Manufacturing Sites)

PLASTIC MULTI SMALL OUTLINE, 1.20 MM PITCH PACKAGE 1.14 MM PITCH, 15.40 MM BODY WIDTH, RECT FAMILY PACKAGE

PLASTIC BOTTOM GRID ARRAY BALL, 0.80 MM PITCH, SQUARE FAMILY PACKAGE

Part Model Assembly Process Classification Guidelines for Electronic-Device Packages – XML Requirements

Part Model Guidelines for Electronic-Device Packages – XML Requirements

PLASTIC DUAL SMALL OUTLINE, RECTANGULAR FAMILY PACKAGE

Pages

Search by Keyword or Document Number

Filter by committees:

Filter by document type:

Filter by keywords: