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Title	Document #	Date
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS This is an editorial revision, details can be found in Annex F.	JEP162A.01	Jan 2021
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST	JESD22-A101D.01	Jan 2021
This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DDR4 NVDIMM-P BUSS PROTOCOL	JESD304-4	Nov 2020
TEMPORARILY REMOVED 12/8/20. If your downloaded proir to this date please discard this iwill be republished shortly as JESD304-4.01An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6
Annex A, R/C A, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Unbuffered DIMM Design Specification Release Number: 30A	MODULE4.20.26.A	Nov 2020
This document defines the electrical and mechanical requirements for Raw Card A, 288-pin, 1.2 Volt (VDD), Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM UDIMMs). These DDR4 Unbuffered DIMMs (UDIMMs) are intended for use as main memory when installed in PCs. Committee Item 2231.38A. Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package	TO-220L.01	Nov 2020
Item 11.10-456(E) Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 6 Release Number: 30	SPD4.1.2.L-6	Nov 2020
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H. Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Plastic Quad Flatpack, 0.65 mm Pitch, 3.30 mm Body, Square Family Package	MO-346A	Nov 2020
Designator: PQFP-B#[#]_I0p65... Item: 11.11-981, Access STP Files for MO-346A Cross Reference: N/A Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0	JESD220-2B	Nov 2020
This standard specifies the characteristics of the UFS card electrical interface and the memory device. This document defines the added/modified features in UFS card compared to embedded UFS device. For other common features JESD220, UFS, will be referenced. Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-64.1 Available for purchase: $76.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
TEMPERATURE CYCLING	JESD22-A104F	Nov 2020
This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses. Committee(s): JC-14.1 Free download. Registration or login required.
CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST	JESD22-A100E	Nov 2020
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES	JEP167A	Nov 2020
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required.
DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD	JESD404-1	Nov 2020
Definition for all DDRx component documents to reference. This is generic to any DDRxtechnology. Item 1842.34 Committee(s): JC-42.3C Free download. Registration or login required.
Standard - Plastic Dual Small Outline, 1.27 mm pitch, 7.50 mm Body Width Rectangular Package Family	MS-013G	Oct 2020
Designator: PDSO-G#-I1p27... Item 11.11-967(S). Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC MODULE SIDEBAND BUS (SidebandBus)	JESD403-1	Oct 2020
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C. Committee(s): JC-45 Free download. Registration or login required.
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick	MO-345A	Oct 2020
Designator: PDSO-G#_I0P5-##... Item: 11.11-984, Access STP Files for MO-345A Cross Reference: SO-023, GS-010C Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
JEDEC Manual of Organization and Procedure	JM21T	Oct 2020
The mission of JEDEC is to serve the solid state industry by creating, publishing, and promoting global acceptance of standards, and by providing a forum for technical exchange on leading industry topics. This manual provides guidance for JEDEC members and staff to perform their functions correctly in the standardization process. Committee(s): JC-BOD Free download. Registration or login required.
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements	JEP181	Sep 2020
This standard establishes the requirements for the exchange of electronic thermal system level simulation models between supplier and end user in a single neutral file format. The data is held in an XML format, conforming to an XML schema that this document describes. Get the XML Schema: JEP181_Schema_R1p0. Committee(s): JC-15 Free download. Registration or login required.
Standard - Plastic Dual Small Outline (SO) Gull Wing, 1.27 mm Pitch Package	MS-012G.02	Sep 2020
Designator: PDSO-G#_I127-##... Item 11.11-972(E), Minor editorial correction. Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 12 Pin UFS Card, 0.91 mm Pitch	MO-320B	Sep 2020
Designator: PBMA-N11-I0p91-CturZ1p0 Item 11.11-985 Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Dual Small Outline Gull Wing Package, 1.10 mm Thick	MO-193F	Sep 2020
Designator: PDSO-G#_I0P##-##... Item 11.11-983 Committee(s): JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.

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