Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
STANDARD MANUFACTURER'S IDENTIFICATION CODE |
JEP106BL | Feb 2025 |
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to https://www.jedec.org/standards-documents/id-codes-order-form Free download. Registration or login required. |
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Universal Flash Storage (UFS)Release Number: Version 4.1 |
JESD220G | Dec 2024 |
This document replaces all prior versions; however, JESD220F August 2022 (version 4.0) remains available for reference purposes. This standard defines a UFS Universal Flash Storage electrical interface and a UFS memory device. Available for purchase: $423.00 Add to Cart Paying JEDEC Members may login for free access. |
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Universal Flash Storage Host Controller Interface (UFSHCI)Release Number: Version 4.1 |
JESD223F | Dec 2024 |
This document replaces all prior versions; however, JESD223E August 2022 (version 4.0) remains available for reference purposes. This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Clause 4 provides a brief overview of the architectural overview of UFS. Clause 5 describes the register interface of UFSHCI. Clause 6 describes the data structure used by UFSHCI. Clause 7 provides a theory of operation for UFSHCI. Clause 8 describes the error recovery process for UFSHCI. Available for purchase: $220.00 Add to Cart Paying JEDEC Members may login for free access. |
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Serial Flash Discoverable Parameters (SFDP) |
JESD216G | Nov 2024 |
The SFDP standard defines the structure of the SFDP database within the memory device and methods used to read its data. Committee(s): JC-42.4 Free download. Registration or login required. |
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LPDDR5/5X Serial Presence Detect (SPD) ContentsRelease Number: 1.0 |
JESD406-5A | Nov 2024 |
This publication describes the serial presence detect (SPD) values for all LPDDR5/5X memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. The storage capacity of the SPD non-volatile memory is limited, so a number of techniques are employed to optimize the use of these bytes, including overlays and run length limited coding. Committee(s): JC-45 Free download. Registration or login required. |
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DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTSRelease Number: Release 1.3 |
JESD400-5C | Sep 2024 |
This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. Committee(s): JC-45 Free download. Registration or login required. |
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JEDEC® Memory Module Label – for Compute Express Link® (CXL®)Release Number: 1.1 |
JESD405-1B | Jun 2024 |
This standard defines the labels that shall be applied to all CXL memory modules to fully describe the key attributes of the module. The label can be in the form of a stick-on label, silk screened onto the assembly, or marked using an alternate customer-readable format. Committee(s): JC-45 Free download. Registration or login required. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD |
JESD232A.01 | Mar 2023 |
Terminology update. This standard defines the Graphics Double Data This standard defines the GDDR5X SGRAM memory standard, including features, device operation, electrical characteristics, timings, signal pin assignments, and package Committee(s): JC-42.3, JC-42.3C Free download. Registration or login required. |
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RADIO FRONT END - BASEBAND (RF-BB) INTERFACE |
JESD96A.01 | Mar 2023 |
Terminology update. This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC). Committee(s): JC-61 Free download. Registration or login required. |
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