Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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144 Pin DRAM SO-DIMM |
MODULE4.5.5 | Mar 1999 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin DDR SGRAM SO-DIMM |
MODULE4.5.9 | Mar 1999 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM |
MODULE4.5.13 | Oct 2000 |
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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112 Pin MPDRAM DIMM |
MODULE4.4.6 | Jun 1997 |
Release No.9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification |
MODULE4.20.9 | Nov 2004 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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100 Pin DRAM, SDRAM, and ROM DIMM |
MODULE4.4.8 | Dec 1997 |
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE |
JESD8-31 | Mar 2018 |
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.8 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.8 V. Committee(s): JC-16 Free download. Registration or login required. |
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1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE |
JESD8-26 | Sep 2011 |
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required. |
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1.2 V +/- 0.1 V (NORMAL RANGE) AND 0.8 - 1.3 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUITS: |
JESD8-12A.01 | Sep 2007 |
This standard defines power supply voltage ranges, dc interface and switching parameters for a high speed, low voltage family of nonterminated digital circuits driving/driven by parts of the same family, or mixed families which comply with the input receiver specifications. The specifications in this standard represent a minimum set of interface specifications for CMOS compatible circuits. Committee(s): JC-16 Free download. Registration or login required. |
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1.05 V CMOS |
JESD8-34 | Apr 2020 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01 Committee(s): JC-16 Free download. Registration or login required. |