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Title	Document #	Date
DDR5 SDRAM Release Number: Version 1.2	JESD79-5B	Aug 2022
This standard defines the DDR5 SDRAM Specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8 Gb through 32 Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3, and LPDDR4 standards (JESD79, JESD79-2, JESD79-3, and JESD209-4). Item 1848.99M. Committee(s): JC-42.3B Available for purchase: $369.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Universal Flash Storage (UFS) File Based Optimizations (FBO) Extension, Version 1.0	JESD231	Aug 2022
This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called File Based Optimization (FBO), in UFS specification. It also provides some details in how to utilize the FBO for gaining higher performance in UFS devices. Committee(s): JC-64.1 Free download. Registration or login required.
Universal Flash Storage Host Controller Interface (UFSHCI), Version 4.0	JESD223E	Aug 2022
This standard describes a functional specification of the Host Controller Interface (HCI) for Universal Flash Storage (UFS). The objective of UFSHCI is to provide a uniform interface method of accessing the UFS hardware capabilities so that a standard/common Driver can be provided for the Host Controller. The common Driver would work with UFS host controller from any vendor. This standard includes a description of the hardware/software interface between system software and the host controller hardware. It is intended for hardware designers, system builders and software developers. This standard is a companion document to [UFS], Universal Flash Storage (UFS). The reader is assumed to be familiar with [UFS], [MIPI-UNIPRO], and [MIPI-M-PHY]. Item 206.25 Committee(s): JC-64.1 Available for purchase: $163.00 Add to Cart Paying JEDEC Members may login for free access.
UNIVERSAL FLASH STORAGE, Version 4.0	JESD220F	Aug 2022
This document replaces all past versions, however JESD220E, January 2020 (V 3.1), is available for reference only. This standard specifies the characteristics of the UFS electrical interface and the memory device. Such characteristics include (among others) low power consumption, high data throughput, low electromagnetic interference and optimization for mass memory subsystem efficiency. The UFS electrical interface is based on an advanced differential interface by MIPI M-PHY specification which together with the MIPI UniPro specification forms the interconnect of the UFS interface. Committee(s): JC-64.1 Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex B Release Number: Version 1.0	JESD308-U0-RCB	Jul 2022
This annex JESD308-U0-RCB, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card B Annex defines the design detail of x8, 2 Package Ranks DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.11A Committee(s): JC-45.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex E Release Number: Version 1.0	JESD308-U4-RCE	Jul 2022
This annex JESD308-U4-RCE, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) with 4-bit ECC (EC4 SODIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 ECC UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.12A Committee(s): JC-45.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex A Release Number: Version 1.0	JESD308-U0-RCA	Jul 2022
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex A Release Number: Version 1.0	JESD308-U0-RCA	Jul 2022
This annex JESD308-U0-RCA, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Raw Card AAnnex defines the design detail of x8, 1 Package Rank DDR5 UDIMM. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.13A Committee(s): JC-45.3 Free download. Registration or login required.
DDR5 UDIMM Raw Card Annex D Release Number: Version 1.0	JESD308-U4-RCD	Jul 2022
This annex JESD308-U4-RCD, DDR5 Unbuffered Dual Inline Memory Module with 4-bit ECC (EC4UDIMM) Raw Card D Annex defines the design detail of x8, 1 Package Rank DDR5 UDIMM with 4-bit ECC. The common feature of DDR5 UDIMM such as the connector pinout can be found in the JESD308, DDR5 Unbuffered Dual Inline Memory Module (UDIMM) Common Standard. Item 2265.14A Free download. Registration or login required.

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