Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2022 | Jun 2023 |
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Free download. Registration or login required. |
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GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTSStatus: Reaffirmed May 2023 |
JEP142 | May 2023 |
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Free download. Registration or login required. |
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Graphics Double Data Rate (GDDR6) SGRAM Standard |
JESD250D | May 2023 |
This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDR6 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDR6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the GDDR5 Standard (JESD212). Committee(s): JC-42.3C Free download. Registration or login required. |
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Statistical Process Control Systems |
JESD557D | May 2023 |
This standard specifies the general requirements of a statistical process control (SPC) system. This is a revision of JESD557C. Committee(s): JC-14 Free download. Registration or login required. |
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Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification |
JEP114A | May 2023 |
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Free download. Registration or login required. |
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Guidelines for Supplier Performance Rating |
JEP146B | May 2023 |
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Free download. Registration or login required. |
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NAND Flash Interface Interoperability |
JESD230F.01 | May 2023 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42.4 Free download. Registration or login required. |
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HYBRIDS/MCM |
JESD93A | May 2023 |
This specification establishes the general requirements for hybrid microcircuits, RF/microwave hybrid microcircuits and MCMs (hereafter referred to as devices). Detailed performance requirements for a specific device are specified in the applicable device acquisition document. In the event of a conflict between this document and the device acquisition document, the device acquisition document will take precedence. Committee(s): JC-14.3 Free download. Registration or login required. |
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DDR5 Clock Driver Definition (DDR5CK01) |
JESD82-531 | May 2023 |
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CK01 Device ID is DID = 0x0531. (5 = DDR5, 3= Clock Driver, 1= rev 01). Committee(s): JC-40.4 Free download. Registration or login required. |
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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARDRelease Number: Version 1.5.1 |
JESD300-5B.01 | May 2023 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard. Committee(s): JC-40.1 Free download. Registration or login required. |
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