Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
Registration - Plastic Dual Small Outline Surface, 2 Terminal, Wettable Flank Package |
MO-343A | Mar 2020 |
Designator: PDSO-N2-I#-R#x#Z#-CturET0p04 Patents(): Nexperia BV: US8809121 B2 Committee(s): JC-11.11 Free download. Registration or login required. |
||
Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1A | Mar 2020 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58F Committee(s): JC-42.3C Free download. Registration or login required. |
||
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES |
JEP180 | Feb 2020 |
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required. |
||
EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES |
JESD251A | Feb 2020 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395. Committee(s): JC-42.4 Free download. Registration or login required. |
||
SPD5118, SPD5108 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARD |
JESD300-5 | Feb 2020 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a master host bus. The designations SPD5118 and SPD5108 refer to the families of devices specified by this document. The term SPD5 Hub refers generically to both devices in the family. Committee Item 1852.07F. Committee(s): JC-42.4 Free download. Registration or login required. |
||
Registration - Plastic Bottom Ball Grid Array, 0.75 mm Pitch Rectangular Family Package |
MO-328B | Feb 2020 |
Designator: PBGA-B#[#]_I0p75... Committee(s): JC-11.11 Free download. Registration or login required. |
||
Registration - Plastic Bottom Grid Array Ball, 0.80 mm X 0.65 mm Pitch Rectangular Family Package |
MO-311E | Feb 2020 |
Designator: PBGA-B#[#]_I0p65... Committee(s): JC-11.11 Free download. Registration or login required. |
||
Registration - Plastic Bottom Grid Array Ball, 0.65 mm Pitch Square Family Package |
MO-342A | Jan 2020 |
Designator: PBGA-B#[#}_I0p65 Committee(s): JC-11.11 Free download. Registration or login required. |
||
CUSTOMER NOTIFICATION PROCESS FOR DISASTERS |
JESD246A | Jan 2020 |
This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within. Committee(s): JC-14.4 Free download. Registration or login required. |
||
UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 1.0 |
JESD220-3 | Jan 2020 |
This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 135.29A Patents(): WD: 9,323,657 Committee(s): JC-64.1 Available for purchase: $76.00 Add to Cart Paying JEDEC Members may login for free access. |
||
