Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces |
JEP196 | Nov 2023 |
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Free download. Registration or login required. |
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Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices |
JEP197 | Nov 2023 |
This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices. Free download. Registration or login required. |
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Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices |
JEP198 | Nov 2023 |
This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches. Free download. Registration or login required. |
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Procedure for Reliability Characterization of Metal-Insulator-Metal Capacitors |
JEP199 | Apr 2024 |
This document defines the standards for achieving Reliability certification and qualification of on-chip MIM Capacitors and MIS Trench Capacitors. Free download. Registration or login required. |
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PART MODEL SCHEMAS |
JEP30-10v7-0-0 | Nov 2024 |
This download includes all files under the parent schema JEP30-10v7-0-0 (Committees: JC-11, JC-11.2) including:
This will enable the user to validate the schemas. For more information visit the main JEP30 webpage. Committee(s): JC-11, JC-11.2, JC-14, JC-15, JC-16 Free download. Registration or login required. |
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Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices Volume 1 |
JEP200 | Jun 2024 |
This document provides guidelines for test methods and circuits to be used for measuring switching energy loss due to output capacitance hysteresis in semiconductor power devices. Committee(s): JC-70, JC-70.1, JC-70.2 Free download. Registration or login required. |
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Guidelines for Reverse Recovery Time and Charge Measurement of SiC MOSFET Version 1.0 |
JEP201 | Aug 2024 |
This guideline is intended to overcome the limitations of prior standards and provide a test circuit and method that provides both reliable and repeatable results. Free download. Registration or login required. |
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Guidelines for Representing Threshold Voltage of SiC MOSFETs in Datasheets, Version 1.0Release Number: Version 1.0 |
JEP202 | Jan 2025 |
This publication provides guidelines for representation of threshold voltage and transfer characteristic of SiC MOS device in datasheets. Free download. Registration or login required. |
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JOINT IPC/JEDEC Standard for Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Devices |
J-STD-035A | Dec 2022 |
This method provides users with an acoustic microscopy process flow for detecting anomalies (delaminations, cracks, mold compound voids, etc.) nondestructively in encapsulated electronic devices while achieving reproducibility. Free download. Registration or login required. |
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JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES |
J-STD-033D | Apr 2018 |
The purpose of this document is to provide manufacturers and users with standardized methods for handling, packing, shipping, and use of moisture/reflow and process sensitive devices that have been classified to the levels defined in J-STD-020 or J-STD-075. These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and damage-free reflow can be achieved. The dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date. Free download. Registration or login required. |