Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # | Date |
|---|---|---|
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS |
JEP178 | Apr 2021 |
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required. |
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COPY-EXACT PROCESS FOR MANUFACTURING |
JEP185 | Aug 2021 |
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required. |
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Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0 |
JEP186 | Dec 2021 |
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required. |
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Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets |
JEP187 | Dec 2021 |
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required. |
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ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema |
JEP181_Schema_R2p0 | Nov 2023 |
In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”. Committee(s): JC-15 Free download. Registration or login required. |
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Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0 |
JEP190 | Aug 2022 |
This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup. Committee(s): JC-70.2 Free download. Registration or login required. |
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SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED) |
JEP164 | Oct 2022 |
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required. |
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Survey On Latch-Up Testing Practices and Recommendations for Improvements |
JEP193 | Jan 2023 |
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Free download. Registration or login required. |
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Guidelines for Gate Charge (QG) Test Method for SiC MOSFET |
JEP192 | Jan 2023 |
This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. Free download. Registration or login required. |
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Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs |
JEP194 | Feb 2023 |
This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric. Free download. Registration or login required. |
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